Commit 8e180390 authored by Thomas Bogendoerfer's avatar Thomas Bogendoerfer
Browse files

MIPS: Remove unused shadow GPR support from vector irq setup 



Using shadow GPRs for vectored interrupts has never been used,
time to remove it.

Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 682fb5be

arch/mips/kernel/traps.c

+27 −61
Original line number Diff line number Diff line
@@ -2055,53 +2055,47 @@ static void do_default_vi(void) 
	panic("Caught unexpected vectored interrupt.");

}



static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)

void *set_vi_handler(int n, vi_handler_t addr)

{

	extern const u8 except_vec_vi[];

	extern const u8 except_vec_vi_ori[], except_vec_vi_end[];

	extern const u8 rollback_except_vec_vi[];

	unsigned long handler;

	unsigned long old_handler = vi_handlers[n];

	int srssets = current_cpu_data.srsets;

	u16 *h;

	unsigned char *b;

	const u8 *vec_start;

	int ori_offset;

	int handler_len;



	BUG_ON(!cpu_has_veic && !cpu_has_vint);



	if (addr == NULL) {

		handler = (unsigned long) do_default_vi;

		srs = 0;

	} else

		handler = (unsigned long) addr;

	vi_handlers[n] = handler;



	b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);



	if (srs >= srssets)

		panic("Shadow register set %d not supported", srs);



	if (cpu_has_veic) {

		if (board_bind_eic_interrupt)

			board_bind_eic_interrupt(n, srs);

			board_bind_eic_interrupt(n, 0);

	} else if (cpu_has_vint) {

		/* SRSMap is only defined if shadow sets are implemented */

		if (srssets > 1)

			change_c0_srsmap(0xf << n*4, srs << n*4);

			change_c0_srsmap(0xf << n*4, 0 << n*4);

	}



	if (srs == 0) {

		/*

		 * If no shadow set is selected then use the default handler

		 * that does normal register saving and standard interrupt exit

		 */

		extern const u8 except_vec_vi[];

		extern const u8 except_vec_vi_ori[], except_vec_vi_end[];

		extern const u8 rollback_except_vec_vi[];

		const u8 *vec_start = using_rollback_handler() ?

				      rollback_except_vec_vi : except_vec_vi;

	vec_start = using_rollback_handler() ? rollback_except_vec_vi :

					       except_vec_vi;

#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)

		const int ori_offset = except_vec_vi_ori - vec_start + 2;

	ori_offset = except_vec_vi_ori - vec_start + 2;

#else

		const int ori_offset = except_vec_vi_ori - vec_start;

	ori_offset = except_vec_vi_ori - vec_start;

#endif

		const int handler_len = except_vec_vi_end - vec_start;

	handler_len = except_vec_vi_end - vec_start;



	if (handler_len > VECTORSPACING) {

		/*
@@ -2122,38 +2116,10 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 
	*h = n * sizeof(handler);

	local_flush_icache_range((unsigned long)b,

				 (unsigned long)(b+handler_len));

	}

	else {

		/*

		 * In other cases jump directly to the interrupt handler. It

		 * is the handler's responsibility to save registers if required

		 * (eg hi/lo) and return from the exception using "eret".

		 */

		u32 insn;



		h = (u16 *)b;

		/* j handler */

#ifdef CONFIG_CPU_MICROMIPS

		insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);

#else

		insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);

#endif

		h[0] = (insn >> 16) & 0xffff;

		h[1] = insn & 0xffff;

		h[2] = 0;

		h[3] = 0;

		local_flush_icache_range((unsigned long)b,

					 (unsigned long)(b+8));

	}



	return (void *)old_handler;

}



void *set_vi_handler(int n, vi_handler_t addr)

{

	return set_vi_srs_handler(n, addr, 0);

}



extern void tlb_init(void);



/*