Commit 8e1cd40d authored by Khaled Almahallawy's avatar Khaled Almahallawy Committed by Jani Nikula
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drm/i915/dp: Use LINK_QUAL_PATTERN_* Phy test pattern names 



Starting from DP2.0 specs, DPCD 248h is renamed
LINK_QUAL_PATTERN_SELECT and it has the same values of registers
DPCD 10Bh-10Eh.
Use the PHY pattern names defined for DPCD 10Bh-10Eh in order to add
CP2520 Pattern 3 (TPS4) phy pattern support in the next
patch of this series and DP2.1 PHY patterns for future series.

v2: rebase

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Lee Shawn C <shawn.c.lee@intel.com>
Signed-off-by: default avatarKhaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231213211542.3585105-1-khaled.almahallawy@intel.com
parent 47cdb66a

drivers/gpu/drm/i915/display/intel_dp.c

+6 −6
Original line number Diff line number Diff line
@@ -4683,27 +4683,27 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 
	u32 pattern_val;



	switch (data->phy_pattern) {

	case DP_PHY_TEST_PATTERN_NONE:

	case DP_LINK_QUAL_PATTERN_DISABLE:

		drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");

		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);

		break;

	case DP_PHY_TEST_PATTERN_D10_2:

	case DP_LINK_QUAL_PATTERN_D10_2:

		drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");

		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),

			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);

		break;

	case DP_PHY_TEST_PATTERN_ERROR_COUNT:

	case DP_LINK_QUAL_PATTERN_ERROR_RATE:

		drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");

		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),

			       DDI_DP_COMP_CTL_ENABLE |

			       DDI_DP_COMP_CTL_SCRAMBLED_0);

		break;

	case DP_PHY_TEST_PATTERN_PRBS7:

	case DP_LINK_QUAL_PATTERN_PRBS7:

		drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");

		intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),

			       DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);

		break;

	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:

	case DP_LINK_QUAL_PATTERN_80BIT_CUSTOM:

		/*

		 * FIXME: Ideally pattern should come from DPCD 0x250. As

		 * current firmware of DPR-100 could not set it, so hardcoding
@@ -4721,7 +4721,7 @@ static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 
			       DDI_DP_COMP_CTL_ENABLE |

			       DDI_DP_COMP_CTL_CUSTOM80);

		break;

	case DP_PHY_TEST_PATTERN_CP2520:

	case DP_LINK_QUAL_PATTERN_CP2520_PAT_1:

		/*

		 * FIXME: Ideally pattern should come from DPCD 0x24A. As

		 * current firmware of DPR-100 could not set it, so hardcoding