Commit 8e357802 authored by Matthew Auld's avatar Matthew Auld Committed by Rodrigo Vivi
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drm/xe/mocs: update MOCS table for xe2 



Looks like there were some changes at some point here for preferring L4
uncached for some of the indexes. Triple checked the PAT settings also,
but that looks all correct as per current BSpec.

BSpec: 71582
Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 975e4a37

drivers/gpu/drm/xe/xe_mocs.c

+5 −5
Original line number Diff line number Diff line
@@ -366,9 +366,9 @@ static const struct xe_mocs_entry mtl_mocs_desc[] = { 


static const struct xe_mocs_entry xe2_mocs_table[] = {

	/* Defer to PAT */

	MOCS_ENTRY(0, XE2_L3_0_WB | L4_0_WB, 0),

	/* Cached L3 + L4 */

	MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),

	MOCS_ENTRY(0, XE2_L3_0_WB | L4_3_UC, 0),

	/* Cached L3, Uncached L4 */

	MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_3_UC, 0),

	/* Uncached L3, Cached L4 */

	MOCS_ENTRY(2, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0),

	/* Uncached L3 + L4 */
@@ -390,8 +390,8 @@ static unsigned int get_mocs_settings(struct xe_device *xe, 
		info->table = xe2_mocs_table;

		info->n_entries = XE2_NUM_MOCS_ENTRIES;

		info->uc_index = 3;

		info->wb_index = 1;

		info->unused_entries_index = 1;

		info->wb_index = 4;

		info->unused_entries_index = 4;

		break;

	case XE_PVC:

		info->size = ARRAY_SIZE(pvc_mocs_desc);