Commit 8e401ff5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.18-2022-04-13' of...

Merge tag 'amd-drm-fixes-5.18-2022-04-13' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.18-2022-04-13:

amdgpu:
- Fix for alpha properly in pre-multiplied mode
- Fix VCN 3.1.2 firmware name
- Suspend/resume fix
- Add a gfxoff quirk for Mac vega20 board
- DCN 3.1.6 spread spectrum fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220414025821.5811-1-alexander.deucher@amd.com
parents 98a71d12 aadaeca4
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+12 −6
Original line number Diff line number Diff line
@@ -2323,18 +2323,23 @@ static int amdgpu_pmops_suspend(struct device *dev)
{
	struct drm_device *drm_dev = dev_get_drvdata(dev);
	struct amdgpu_device *adev = drm_to_adev(drm_dev);
	int r;

	if (amdgpu_acpi_is_s0ix_active(adev))
		adev->in_s0ix = true;
	else
		adev->in_s3 = true;
	r = amdgpu_device_suspend(drm_dev, true);
	if (r)
		return r;
	return amdgpu_device_suspend(drm_dev, true);
}

static int amdgpu_pmops_suspend_noirq(struct device *dev)
{
	struct drm_device *drm_dev = dev_get_drvdata(dev);
	struct amdgpu_device *adev = drm_to_adev(drm_dev);

	if (!adev->in_s0ix)
		r = amdgpu_asic_reset(adev);
	return r;
		return amdgpu_asic_reset(adev);

	return 0;
}

static int amdgpu_pmops_resume(struct device *dev)
@@ -2575,6 +2580,7 @@ static const struct dev_pm_ops amdgpu_pm_ops = {
	.prepare = amdgpu_pmops_prepare,
	.complete = amdgpu_pmops_complete,
	.suspend = amdgpu_pmops_suspend,
	.suspend_noirq = amdgpu_pmops_suspend_noirq,
	.resume = amdgpu_pmops_resume,
	.freeze = amdgpu_pmops_freeze,
	.thaw = amdgpu_pmops_thaw,
+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@
#define FIRMWARE_ALDEBARAN	"amdgpu/aldebaran_vcn.bin"
#define FIRMWARE_BEIGE_GOBY	"amdgpu/beige_goby_vcn.bin"
#define FIRMWARE_YELLOW_CARP	"amdgpu/yellow_carp_vcn.bin"
#define FIRMWARE_VCN_3_1_2	"amdgpu/vcn_3_1_2_vcn.bin"
#define FIRMWARE_VCN_3_1_2	"amdgpu/vcn_3_1_2.bin"

MODULE_FIRMWARE(FIRMWARE_RAVEN);
MODULE_FIRMWARE(FIRMWARE_PICASSO);
+2 −0
Original line number Diff line number Diff line
@@ -1205,6 +1205,8 @@ static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = {
	{ 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 },
	/* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */
	{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 },
	/* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */
	{ 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 },
	{ 0, 0, 0, 0, 0 },
};

+1 −1
Original line number Diff line number Diff line
@@ -374,7 +374,7 @@ void dce_clock_read_ss_info(struct clk_mgr_internal *clk_mgr_dce)
				clk_mgr_dce->dprefclk_ss_percentage =
						info.spread_spectrum_percentage;
			}
			if (clk_mgr_dce->base.ctx->dc->debug.ignore_dpref_ss)
			if (clk_mgr_dce->base.ctx->dc->config.ignore_dpref_ss)
				clk_mgr_dce->dprefclk_ss_percentage = 0;
		}
	}
+2 −2
Original line number Diff line number Diff line
@@ -686,8 +686,8 @@ void dcn316_clk_mgr_construct(
	clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
 	clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
	dce_clock_read_ss_info(&clk_mgr->base);
	clk_mgr->base.dccg->ref_dtbclk_khz =
	dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
	/*clk_mgr->base.dccg->ref_dtbclk_khz =
	dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);*/

	clk_mgr->base.base.bw_params = &dcn316_bw_params;

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