Commit 8e40dd93 authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: Revert "not disable dtb as dto src at dpms off" 



[why]
not all the asic using the same code path.
need to revisit and limit the impact.

This reverts commit 32be4e39.

Reviewed-by: default avatarGabe Teeger <gabe.teeger@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Signed-off-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1594b60d

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

+5 −0
Original line number Diff line number Diff line
@@ -1152,6 +1152,7 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 
	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

	struct dccg *dccg = dc->res_pool->dccg;

	struct timing_generator *tg = pipe_ctx->stream_res.tg;

	struct dtbclk_dto_params dto_params = {0};

	int dp_hpo_inst;

	struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc;

	struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
@@ -1178,10 +1179,14 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 
	link_hwss->reset_stream_encoder(pipe_ctx);



	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

		dto_params.otg_inst = tg->inst;

		dto_params.timing = &pipe_ctx->stream->timing;

		dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

		if (dccg) {

			dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

			dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

			if (dccg && dccg->funcs->set_dtbclk_dto)

				dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

		}

	} else if (dccg && dccg->funcs->disable_symclk_se) {

		dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

+0 −8
Original line number Diff line number Diff line
@@ -2806,8 +2806,6 @@ void dcn20_reset_back_end_for_pipe( 
{

	struct dc_link *link = pipe_ctx->stream->link;

	const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);

	struct dccg *dccg = dc->res_pool->dccg;

	struct dtbclk_dto_params dto_params = {0};



	DC_LOGGER_INIT(dc->ctx->logger);

	if (pipe_ctx->stream_res.stream_enc == NULL) {
@@ -2868,12 +2866,6 @@ void dcn20_reset_back_end_for_pipe( 
					&pipe_ctx->link_res, pipe_ctx->stream->signal);

			link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;

		}

		if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) {

			dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;

			dto_params.timing = &pipe_ctx->stream->timing;

			if (dccg && dccg->funcs->set_dtbclk_dto)

				dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

		}

	}



/*