Commit 8e5f17e6 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-imx-5.14' of... 

Merge tag 'clk-imx-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Remove audio ipg clock from i.MX8MP
 - Fix naming typo of clock compatible string
 - Remove deprecated legacy clock binding for SCU clock driver
 - Use common clk-imx8qxp for both i.MX8QXP and i.MX8QM
 - Add multiple clocks to clk-imx8qxp driver (enet, hdmi, lcdif, audio,
   parallel interface)
 - Add dedicated clock ops for paralel interface
 - Different fixes for clocks controlled by ATF
 - Fix different issues related to parallel interface clocks
 - Add A53/A72 frequency scaling support clk-scu driver
 - Add special case for DCSS clock on suspend for clk-scu driver
 - Add parent save/restore on suspend/resume to clk-scu driver
 - Skip runtime PM enablement for CPU clocks in clk-scu driver
 - Remove the sys1_pll/sys2_pll clock gates for i.MX8MQ and their
   bindings

* tag 'clk-imx-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  clk: imx8mq: remove SYS PLL 1/2 clock gates
  clk: imx: scu: Do not enable runtime PM for CPU clks
  clk: imx: scu: add parent save and restore
  clk: imx: scu: Only save DC SS clock using non-cached clock rate
  clk: imx: scu: Add A72 frequency scaling support
  clk: imx: scu: Add A53 frequency scaling support
  clk: imx: scu: bypass pi_pll enable status restore
  clk: imx: scu: detach pd if can't power up
  clk: imx: scu: bypass cpu clock save and restore
  clk: imx: scu: add parallel port clock ops
  clk: imx: scu: add more scu clocks
  clk: imx: scu: add enet rgmii gpr clocks
  clk: imx8qm: add clock valid resource checking
  clk: imx8qxp: add clock valid checking mechnism
  clk: imx: scu: add gpr clocks support
  clk: imx: scu: remove legacy scu clock binding support
  dt-bindings: arm: imx: scu: drop deprecated legacy clock binding
  dt-bindings: arm: imx: scu: fix naming typo of clk compatible string
  clk: imx: Remove the audio ipg clock from imx8mp
parents 6efb943b c586f53a

Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

+4 −6
Original line number Diff line number Diff line
@@ -86,13 +86,11 @@ This binding uses the common clock binding[1]. 


Required properties:

- compatible:		Should be one of:

			  "fsl,imx8qm-clock"

			  "fsl,imx8qxp-clock"

			  "fsl,imx8qm-clk"

			  "fsl,imx8qxp-clk"

			followed by "fsl,scu-clk"

- #clock-cells:		Should be either

			2: Contains the Resource and Clock ID value.

			or

			1: Contains the Clock ID value. (DEPRECATED)

- #clock-cells:		Should be 2.

			Contains the Resource and Clock ID value.

- clocks:		List of clock specifiers, must contain an entry for

			each required entry in clock-names

- clock-names:		Should include entries "xtal_32KHz", "xtal_24MHz"

drivers/clk/imx/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -27,7 +27,8 @@ obj-$(CONFIG_CLK_IMX8MP) += clk-imx8mp.o 
obj-$(CONFIG_CLK_IMX8MQ) += clk-imx8mq.o



obj-$(CONFIG_MXC_CLK_SCU) += clk-imx-scu.o clk-imx-lpcg-scu.o

clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o

clk-imx-scu-$(CONFIG_CLK_IMX8QXP) += clk-scu.o clk-imx8qxp.o \

				     clk-imx8qxp-rsrc.o clk-imx8qm-rsrc.o

clk-imx-lpcg-scu-$(CONFIG_CLK_IMX8QXP) += clk-lpcg-scu.o clk-imx8qxp-lpcg.o



obj-$(CONFIG_CLK_IMX1)   += clk-imx1.o

drivers/clk/imx/clk-imx8mp.c

+0 −1
Original line number Diff line number Diff line
@@ -556,7 +556,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev) 
	hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);



	hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);

	hws[IMX8MP_CLK_IPG_AUDIO_ROOT] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1);



	hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);

	hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);

drivers/clk/imx/clk-imx8mq.c

+18 −38
Original line number Diff line number Diff line
@@ -358,46 +358,26 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 
	hws[IMX8MQ_VIDEO2_PLL_OUT] = imx_clk_hw_sscg_pll("video2_pll_out", video2_pll_out_sels, ARRAY_SIZE(video2_pll_out_sels), 0, 0, 0, base + 0x54, 0);



	/* SYS PLL1 fixed output */

	hws[IMX8MQ_SYS1_PLL_40M_CG] = imx_clk_hw_gate("sys1_pll_40m_cg", "sys1_pll_out", base + 0x30, 9);

	hws[IMX8MQ_SYS1_PLL_80M_CG] = imx_clk_hw_gate("sys1_pll_80m_cg", "sys1_pll_out", base + 0x30, 11);

	hws[IMX8MQ_SYS1_PLL_100M_CG] = imx_clk_hw_gate("sys1_pll_100m_cg", "sys1_pll_out", base + 0x30, 13);

	hws[IMX8MQ_SYS1_PLL_133M_CG] = imx_clk_hw_gate("sys1_pll_133m_cg", "sys1_pll_out", base + 0x30, 15);

	hws[IMX8MQ_SYS1_PLL_160M_CG] = imx_clk_hw_gate("sys1_pll_160m_cg", "sys1_pll_out", base + 0x30, 17);

	hws[IMX8MQ_SYS1_PLL_200M_CG] = imx_clk_hw_gate("sys1_pll_200m_cg", "sys1_pll_out", base + 0x30, 19);

	hws[IMX8MQ_SYS1_PLL_266M_CG] = imx_clk_hw_gate("sys1_pll_266m_cg", "sys1_pll_out", base + 0x30, 21);

	hws[IMX8MQ_SYS1_PLL_400M_CG] = imx_clk_hw_gate("sys1_pll_400m_cg", "sys1_pll_out", base + 0x30, 23);

	hws[IMX8MQ_SYS1_PLL_800M_CG] = imx_clk_hw_gate("sys1_pll_800m_cg", "sys1_pll_out", base + 0x30, 25);



	hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_40m_cg", 1, 20);

	hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_80m_cg", 1, 10);

	hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_100m_cg", 1, 8);

	hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_133m_cg", 1, 6);

	hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_160m_cg", 1, 5);

	hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_200m_cg", 1, 4);

	hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_266m_cg", 1, 3);

	hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_400m_cg", 1, 2);

	hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_800m_cg", 1, 1);

	hws[IMX8MQ_SYS1_PLL_40M] = imx_clk_hw_fixed_factor("sys1_pll_40m", "sys1_pll_out", 1, 20);

	hws[IMX8MQ_SYS1_PLL_80M] = imx_clk_hw_fixed_factor("sys1_pll_80m", "sys1_pll_out", 1, 10);

	hws[IMX8MQ_SYS1_PLL_100M] = imx_clk_hw_fixed_factor("sys1_pll_100m", "sys1_pll_out", 1, 8);

	hws[IMX8MQ_SYS1_PLL_133M] = imx_clk_hw_fixed_factor("sys1_pll_133m", "sys1_pll_out", 1, 6);

	hws[IMX8MQ_SYS1_PLL_160M] = imx_clk_hw_fixed_factor("sys1_pll_160m", "sys1_pll_out", 1, 5);

	hws[IMX8MQ_SYS1_PLL_200M] = imx_clk_hw_fixed_factor("sys1_pll_200m", "sys1_pll_out", 1, 4);

	hws[IMX8MQ_SYS1_PLL_266M] = imx_clk_hw_fixed_factor("sys1_pll_266m", "sys1_pll_out", 1, 3);

	hws[IMX8MQ_SYS1_PLL_400M] = imx_clk_hw_fixed_factor("sys1_pll_400m", "sys1_pll_out", 1, 2);

	hws[IMX8MQ_SYS1_PLL_800M] = imx_clk_hw_fixed_factor("sys1_pll_800m", "sys1_pll_out", 1, 1);



	/* SYS PLL2 fixed output */

	hws[IMX8MQ_SYS2_PLL_50M_CG] = imx_clk_hw_gate("sys2_pll_50m_cg", "sys2_pll_out", base + 0x3c, 9);

	hws[IMX8MQ_SYS2_PLL_100M_CG] = imx_clk_hw_gate("sys2_pll_100m_cg", "sys2_pll_out", base + 0x3c, 11);

	hws[IMX8MQ_SYS2_PLL_125M_CG] = imx_clk_hw_gate("sys2_pll_125m_cg", "sys2_pll_out", base + 0x3c, 13);

	hws[IMX8MQ_SYS2_PLL_166M_CG] = imx_clk_hw_gate("sys2_pll_166m_cg", "sys2_pll_out", base + 0x3c, 15);

	hws[IMX8MQ_SYS2_PLL_200M_CG] = imx_clk_hw_gate("sys2_pll_200m_cg", "sys2_pll_out", base + 0x3c, 17);

	hws[IMX8MQ_SYS2_PLL_250M_CG] = imx_clk_hw_gate("sys2_pll_250m_cg", "sys2_pll_out", base + 0x3c, 19);

	hws[IMX8MQ_SYS2_PLL_333M_CG] = imx_clk_hw_gate("sys2_pll_333m_cg", "sys2_pll_out", base + 0x3c, 21);

	hws[IMX8MQ_SYS2_PLL_500M_CG] = imx_clk_hw_gate("sys2_pll_500m_cg", "sys2_pll_out", base + 0x3c, 23);

	hws[IMX8MQ_SYS2_PLL_1000M_CG] = imx_clk_hw_gate("sys2_pll_1000m_cg", "sys2_pll_out", base + 0x3c, 25);



	hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_50m_cg", 1, 20);

	hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_100m_cg", 1, 10);

	hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_125m_cg", 1, 8);

	hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_166m_cg", 1, 6);

	hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_200m_cg", 1, 5);

	hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_250m_cg", 1, 4);

	hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_333m_cg", 1, 3);

	hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_500m_cg", 1, 2);

	hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_1000m_cg", 1, 1);

	hws[IMX8MQ_SYS2_PLL_50M] = imx_clk_hw_fixed_factor("sys2_pll_50m", "sys2_pll_out", 1, 20);

	hws[IMX8MQ_SYS2_PLL_100M] = imx_clk_hw_fixed_factor("sys2_pll_100m", "sys2_pll_out", 1, 10);

	hws[IMX8MQ_SYS2_PLL_125M] = imx_clk_hw_fixed_factor("sys2_pll_125m", "sys2_pll_out", 1, 8);

	hws[IMX8MQ_SYS2_PLL_166M] = imx_clk_hw_fixed_factor("sys2_pll_166m", "sys2_pll_out", 1, 6);

	hws[IMX8MQ_SYS2_PLL_200M] = imx_clk_hw_fixed_factor("sys2_pll_200m", "sys2_pll_out", 1, 5);

	hws[IMX8MQ_SYS2_PLL_250M] = imx_clk_hw_fixed_factor("sys2_pll_250m", "sys2_pll_out", 1, 4);

	hws[IMX8MQ_SYS2_PLL_333M] = imx_clk_hw_fixed_factor("sys2_pll_333m", "sys2_pll_out", 1, 3);

	hws[IMX8MQ_SYS2_PLL_500M] = imx_clk_hw_fixed_factor("sys2_pll_500m", "sys2_pll_out", 1, 2);

	hws[IMX8MQ_SYS2_PLL_1000M] = imx_clk_hw_fixed_factor("sys2_pll_1000m", "sys2_pll_out", 1, 1);



	hws[IMX8MQ_CLK_MON_AUDIO_PLL1_DIV] = imx_clk_hw_divider("audio_pll1_out_monitor", "audio_pll1_bypass", base + 0x78, 0, 3);

	hws[IMX8MQ_CLK_MON_AUDIO_PLL2_DIV] = imx_clk_hw_divider("audio_pll2_out_monitor", "audio_pll2_bypass", base + 0x78, 4, 3);

drivers/clk/imx/clk-imx8qm-rsrc.c

0 → 100644
+116 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright 2019-2021 NXP

 *	Dong Aisheng <aisheng.dong@nxp.com>

 */



#include <dt-bindings/firmware/imx/rsrc.h>



#include "clk-scu.h"



/* Keep sorted in the ascending order */

static const u32 imx8qm_clk_scu_rsrc_table[] = {

	IMX_SC_R_A53,

	IMX_SC_R_A72,

	IMX_SC_R_DC_0_VIDEO0,

	IMX_SC_R_DC_0_VIDEO1,

	IMX_SC_R_DC_0,

	IMX_SC_R_DC_0_PLL_0,

	IMX_SC_R_DC_0_PLL_1,

	IMX_SC_R_DC_1_VIDEO0,

	IMX_SC_R_DC_1_VIDEO1,

	IMX_SC_R_DC_1,

	IMX_SC_R_DC_1_PLL_0,

	IMX_SC_R_DC_1_PLL_1,

	IMX_SC_R_SPI_0,

	IMX_SC_R_SPI_1,

	IMX_SC_R_SPI_2,

	IMX_SC_R_SPI_3,

	IMX_SC_R_UART_0,

	IMX_SC_R_UART_1,

	IMX_SC_R_UART_2,

	IMX_SC_R_UART_3,

	IMX_SC_R_UART_4,

	IMX_SC_R_EMVSIM_0,

	IMX_SC_R_EMVSIM_1,

	IMX_SC_R_I2C_0,

	IMX_SC_R_I2C_1,

	IMX_SC_R_I2C_2,

	IMX_SC_R_I2C_3,

	IMX_SC_R_I2C_4,

	IMX_SC_R_ADC_0,

	IMX_SC_R_ADC_1,

	IMX_SC_R_FTM_0,

	IMX_SC_R_FTM_1,

	IMX_SC_R_CAN_0,

	IMX_SC_R_GPU_0_PID0,

	IMX_SC_R_GPU_1_PID0,

	IMX_SC_R_PWM_0,

	IMX_SC_R_PWM_1,

	IMX_SC_R_PWM_2,

	IMX_SC_R_PWM_3,

	IMX_SC_R_PWM_4,

	IMX_SC_R_PWM_5,

	IMX_SC_R_PWM_6,

	IMX_SC_R_PWM_7,

	IMX_SC_R_GPT_0,

	IMX_SC_R_GPT_1,

	IMX_SC_R_GPT_2,

	IMX_SC_R_GPT_3,

	IMX_SC_R_GPT_4,

	IMX_SC_R_FSPI_0,

	IMX_SC_R_FSPI_1,

	IMX_SC_R_SDHC_0,

	IMX_SC_R_SDHC_1,

	IMX_SC_R_SDHC_2,

	IMX_SC_R_ENET_0,

	IMX_SC_R_ENET_1,

	IMX_SC_R_MLB_0,

	IMX_SC_R_USB_2,

	IMX_SC_R_NAND,

	IMX_SC_R_LVDS_0,

	IMX_SC_R_LVDS_0_PWM_0,

	IMX_SC_R_LVDS_0_I2C_0,

	IMX_SC_R_LVDS_0_I2C_1,

	IMX_SC_R_LVDS_1,

	IMX_SC_R_LVDS_1_PWM_0,

	IMX_SC_R_LVDS_1_I2C_0,

	IMX_SC_R_LVDS_1_I2C_1,

	IMX_SC_R_M4_0_I2C,

	IMX_SC_R_M4_1_I2C,

	IMX_SC_R_AUDIO_PLL_0,

	IMX_SC_R_VPU_UART,

	IMX_SC_R_VPUCORE,

	IMX_SC_R_MIPI_0,

	IMX_SC_R_MIPI_0_PWM_0,

	IMX_SC_R_MIPI_0_I2C_0,

	IMX_SC_R_MIPI_0_I2C_1,

	IMX_SC_R_MIPI_1,

	IMX_SC_R_MIPI_1_PWM_0,

	IMX_SC_R_MIPI_1_I2C_0,

	IMX_SC_R_MIPI_1_I2C_1,

	IMX_SC_R_CSI_0,

	IMX_SC_R_CSI_0_PWM_0,

	IMX_SC_R_CSI_0_I2C_0,

	IMX_SC_R_CSI_1,

	IMX_SC_R_CSI_1_PWM_0,

	IMX_SC_R_CSI_1_I2C_0,

	IMX_SC_R_HDMI,

	IMX_SC_R_HDMI_I2S,

	IMX_SC_R_HDMI_I2C_0,

	IMX_SC_R_HDMI_PLL_0,

	IMX_SC_R_HDMI_RX,

	IMX_SC_R_HDMI_RX_BYPASS,

	IMX_SC_R_HDMI_RX_I2C_0,

	IMX_SC_R_AUDIO_PLL_1,

	IMX_SC_R_AUDIO_CLK_0,

	IMX_SC_R_AUDIO_CLK_1,

	IMX_SC_R_HDMI_RX_PWM_0,

	IMX_SC_R_HDMI_PLL_1,

	IMX_SC_R_VPU,

};



const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {

	.rsrc = imx8qm_clk_scu_rsrc_table,

	.num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),

};