Commit 8e63b207 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Dmitry Baryshkov
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drm/msm/dsi/phy: add configuration for SAR2130P 



Qualcomm SAR2130P requires slightly different setup for the DSI PHY. It
is a 5nm PHY (like SM8450), so supplies are the same, but the rest of
the configuration is the same as SM8550 DSI PHY.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarJessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/649257/
Link: https://lore.kernel.org/r/20250418-sar2130p-display-v5-7-442c905cb3a4@oss.qualcomm.com


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
parent 1e7cbfea

drivers/gpu/drm/msm/dsi/phy/dsi_phy.c

+2 −0
Original line number Diff line number Diff line
@@ -581,6 +581,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { 
	  .data = &dsi_phy_7nm_cfgs },

	{ .compatible = "qcom,dsi-phy-7nm-8150",

	  .data = &dsi_phy_7nm_8150_cfgs },

	{ .compatible = "qcom,sar2130p-dsi-phy-5nm",

	  .data = &dsi_phy_5nm_sar2130p_cfgs },

	{ .compatible = "qcom,sc7280-dsi-phy-7nm",

	  .data = &dsi_phy_7nm_7280_cfgs },

	{ .compatible = "qcom,sm6375-dsi-phy-7nm",

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+1 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs; 
extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;

extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;

drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

+23 −0
Original line number Diff line number Diff line
@@ -1289,6 +1289,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = { 
	.quirks = DSI_PHY_7NM_QUIRK_V4_3,

};



const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs = {

	.has_phy_lane = true,

	.regulator_data = dsi_phy_7nm_97800uA_regulators,

	.num_regulators = ARRAY_SIZE(dsi_phy_7nm_97800uA_regulators),

	.ops = {

		.enable = dsi_7nm_phy_enable,

		.disable = dsi_7nm_phy_disable,

		.pll_init = dsi_pll_7nm_init,

		.save_pll_state = dsi_7nm_pll_save_state,

		.restore_pll_state = dsi_7nm_pll_restore_state,

		.set_continuous_clock = dsi_7nm_set_continuous_clock,

	},

	.min_pll_rate = 600000000UL,

#ifdef CONFIG_64BIT

	.max_pll_rate = 5000000000UL,

#else

	.max_pll_rate = ULONG_MAX,

#endif

	.io_start = { 0xae95000, 0xae97000 },

	.num_dsi_phy = 2,

	.quirks = DSI_PHY_7NM_QUIRK_V5_2,

};



const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {

	.has_phy_lane = true,

	.regulator_data = dsi_phy_7nm_98400uA_regulators,