Commit 8e690b81 authored by Kiryl Shutsemau's avatar Kiryl Shutsemau Committed by Paolo Bonzini
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x86/kvm: Override default caching mode for SEV-SNP and TDX 



AMD SEV-SNP and Intel TDX have limited access to MTRR: either it is not
advertised in CPUID or it cannot be programmed (on TDX, due to #VE on
CR0.CD clear).

This results in guests using uncached mappings where it shouldn't and
pmd/pud_set_huge() failures due to non-uniform memory type reported by
mtrr_type_lookup().

Override MTRR state, making it WB by default as the kernel does for
Hyper-V guests.

Signed-off-by: default avatarKirill A. Shutemov <kirill.shutemov@linux.intel.com>
Suggested-by: default avatarBinbin Wu <binbin.wu@intel.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Reviewed-by: default avatarJuergen Gross <jgross@suse.com>
Message-ID: <20241015095818.357915-1-kirill.shutemov@linux.intel.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent bc07eea2

arch/x86/kernel/kvm.c

+4 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ 
#include <asm/apic.h>

#include <asm/apicdef.h>

#include <asm/hypervisor.h>

#include <asm/mtrr.h>

#include <asm/tlb.h>

#include <asm/cpuidle_haltpoll.h>

#include <asm/ptrace.h>
@@ -980,6 +981,9 @@ static void __init kvm_init_platform(void) 
	}

	kvmclock_init();

	x86_platform.apic_post_init = kvm_apic_init;



	/* Set WB as the default cache mode for SEV-SNP and TDX */

	mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK);

}



#if defined(CONFIG_AMD_MEM_ENCRYPT)