Commit 8e98b87f authored by Nuno Sa's avatar Nuno Sa Committed by Jonathan Cameron
Browse files

iio: imu: adis: ensure proper DMA alignment 

Aligning the buffer to the L1 cache is not sufficient in some platforms
as they might have larger cacheline sizes for caches after L1 and thus,
we can't guarantee DMA safety.

That was the whole reason to introduce IIO_DMA_MINALIGN in [1]. Do the same
for the sigma_delta ADCs.

[1]: https://lore.kernel.org/linux-iio/20220508175712.647246-2-jic23@kernel.org/



Fixes: ccd2b52f ("staging:iio: Add common ADIS library")
Signed-off-by: default avatarNuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20240117-adis-improv-v1-1-7f90e9fad200@analog.com


Cc: <Stable@vger.kernel.org>
Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
parent f1dfcbaa

include/linux/iio/imu/adis.h

+2 −1
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 


#include <linux/spi/spi.h>

#include <linux/interrupt.h>

#include <linux/iio/iio.h>

#include <linux/iio/types.h>



#define ADIS_WRITE_REG(reg) ((0x80 | (reg)))
@@ -131,7 +132,7 @@ struct adis { 
	unsigned long		irq_flag;

	void			*buffer;



	u8			tx[10] ____cacheline_aligned;

	u8			tx[10] __aligned(IIO_DMA_MINALIGN);

	u8			rx[4];

};