Commit 8f037e11 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2025-11-04' of... 

Merge tag 'drm-intel-next-2025-11-04' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

drm/i915 feature pull for v6.19:

Features and functionality:
- Enable LNL+ content adaptive sharpness filter (CASF) (Nemesa)
- Use optimized VRR guardband (Ankit, Ville)
- Enable Xe3p LT PHY (Suraj)
- Enable FBC support for Xe3p_LPD display (Sai Teja, Vinod)
- Specify DMC firmware for display version 30.02 (Dnyaneshwar)
- Report reason for disabling PSR to debugfs (Michał)
- Extend i915_display_info with Type-C port details (Khaled)
- Log DSI send packet sequence errors and contents

Refactoring and cleanups:
- Refactoring to prepare for VRR guardband optimization (Ankit)
- Abstract VRR live status wait (Ankit)
- Refactor VRR and DSB timing to handle Set Context Latency explicitly (Ankit)
- Helpers for prefill latency calculations (Ville)
- Refactor SKL+ watermark latency setup (Ville)
- VRR refactoring and cleanups (Ville)
- SKL+ universal plane cleanups (Ville)
- Decouple CDCLK from state->modeset refactor (Ville)
- Refactor VLV/CHV clock functions (Jani)
- Refactor fbdev handling (Jani)
- Call i915 and xe runtime PM from display via function pointers (Jouni)
- IRQ code refactoring  (Jani)
- Drop display dependency on i915 feature check macros (Jani)
- Refactor and unify i915 and xe stolen memory interfaces towards display (Jani)
- Switch to driver agnostic drm to display pointer chase (Jani)
- Use display version over graphics version in display code (Matt A)
- GVT cleanups (Jonathan, Andi)
- Rename a VLV clock function to unify (Michał)
- Explicitly sanitize DMC package header num entries (Luca)
- Remove redundant port clock check from ALPM (Jouni)
- Use sysfs_emit() instead of sprintf() in PMU sysfs (Madhur Kumar)
- Clean up C20 PHY PLL register macros (Imre, Mika))
- Abstract "address in MMIO table" helper for general use (Matt A)
- Improve VRR platform abstractions (Ville)
- Move towards more standard PCI PM code usage (Ville)
- Framebuffer refactoring (Ville)
- Drop display dependency on i915_utils.h (Jani)
- Include cleanups (Jani)

Fixes:
- Workaround docking station DSC issues with high pixel clock and bpp (Imre)
- Fix Panel Replay in DSC mode (Imre)
- Disable tracepoints for PREEMPT_RT as a workaround (Maarten)
- Fix intel_crtc_get_vblank_counter() on PREEMPT_RT (Maarten)
- Fix C10 PHY identification on PTL/WCL (Dnyaneshwar)
- Take AS SDP into account with optimized guardband (Jouni)
- Fix panic structure allocation memory leak (Jani)
- Adjust an FBC workaround platforms (Vinod)
- Add fallback for CDCLK selection (Naladala)
- Avoid using invalid transcoder in MST transport select (Suraj)
- Don't use cursor size reduction on display version 14+ (Nemesa)
- Fix C20 PHY PLL register programming (Imre, Mika)
- Fix PSR frontbuffer flush handling (Jouni)
- Store ALPM parameters in crtc state (Jouni)
- Defeature DRRS on LNL+ (Ville)
- Fix the scope of the large DRAM DIMM workaround (Ville)
- Fix PICA vs. AUX power ordering issue (Gustavo)
- Fix pixel rate for computing watermark line time (Ville)
- Fix framebuffer set_tiling vs. addfb race (Ville)
- DMC event handler fixes (Ville)

DRM Core:
- CRTC sharpness strength property (Nemesa)
- DPCD DSC quirk for Synaptics Panamera devices (Imre)
- Helpers to query the branch DSC max throughput/line-width (Imre)

Merges:
- Backmerge drm-next for v6.18-rc and to sync with drm-xe-next (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/ec5a05f2df6d597a62033ee2d57225cce707b320@intel.com
parents f67d54e9 c4227e16

drivers/gpu/drm/display/drm_dp_helper.c

+156 −0
Original line number Diff line number Diff line
@@ -2552,6 +2552,10 @@ static const struct dpcd_quirk dpcd_quirk_list[] = { 
	{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },

	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */

	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },

	/* Synaptics Panamera supports only a compressed bpp of 12 above 50% of its max DSC pixel throughput */

	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },

	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },

	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },

};



#undef OUI
@@ -2841,6 +2845,158 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S 
}

EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);



/*

 * See DP Standard v2.1a 2.8.4 Minimum Slices/Display, Table 2-159 and

 * Appendix L.1 Derivation of Slice Count Requirements.

 */

static int dsc_sink_min_slice_throughput(int peak_pixel_rate)

{

	if (peak_pixel_rate >= 4800000)

		return 600000;

	else if (peak_pixel_rate >= 2700000)

		return 400000;

	else

		return 340000;

}



/**

 * drm_dp_dsc_sink_max_slice_throughput() - Get a DSC sink's maximum pixel throughput per slice

 * @dsc_dpcd: DSC sink's capabilities from DPCD

 * @peak_pixel_rate: Cumulative peak pixel rate in kHz

 * @is_rgb_yuv444: The mode is either RGB or YUV444

 *

 * Return the DSC sink device's maximum pixel throughput per slice, based on

 * the device's @dsc_dpcd capabilities, the @peak_pixel_rate of the transferred

 * stream(s) and whether the output format @is_rgb_yuv444 or yuv422/yuv420.

 *

 * Note that @peak_pixel_rate is the total pixel rate transferred to the same

 * DSC/display sink. For instance to calculate a tile's slice count of an MST

 * multi-tiled display sink (not considering here the required

 * rounding/alignment of slice count)::

 *

 *   @peak_pixel_rate = tile_pixel_rate * tile_count

 *   total_slice_count = @peak_pixel_rate / drm_dp_dsc_sink_max_slice_throughput(@peak_pixel_rate)

 *   tile_slice_count = total_slice_count / tile_count

 *

 * Returns:

 * The maximum pixel throughput per slice supported by the DSC sink device

 * in kPixels/sec.

 */

int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],

					 int peak_pixel_rate, bool is_rgb_yuv444)

{

	int throughput;

	int delta = 0;

	int base;



	throughput = dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];



	if (is_rgb_yuv444) {

		throughput = (throughput & DP_DSC_THROUGHPUT_MODE_0_MASK) >>

			     DP_DSC_THROUGHPUT_MODE_0_SHIFT;



		delta = ((dsc_dpcd[DP_DSC_RC_BUF_BLK_SIZE - DP_DSC_SUPPORT]) &

			 DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK) >>

			DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT;	/* in units of 2 MPixels/sec */

		delta *= 2000;

	} else {

		throughput = (throughput & DP_DSC_THROUGHPUT_MODE_1_MASK) >>

			     DP_DSC_THROUGHPUT_MODE_1_SHIFT;

	}



	switch (throughput) {

	case 0:

		return dsc_sink_min_slice_throughput(peak_pixel_rate);

	case 1:

		base = 340000;

		break;

	case 2 ... 14:

		base = 400000 + 50000 * (throughput - 2);

		break;

	case 15:

		base = 170000;

		break;

	}



	return base + delta;

}

EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_throughput);



static u8 dsc_branch_dpcd_cap(const u8 dpcd[DP_DSC_BRANCH_CAP_SIZE], int reg)

{

	return dpcd[reg - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0];

}



/**

 * drm_dp_dsc_branch_max_overall_throughput() - Branch device's max overall DSC pixel throughput

 * @dsc_branch_dpcd: DSC branch capabilities from DPCD

 * @is_rgb_yuv444: The mode is either RGB or YUV444

 *

 * Return the branch device's maximum overall DSC pixel throughput, based on

 * the device's DPCD DSC branch capabilities, and whether the output

 * format @is_rgb_yuv444 or yuv422/yuv420.

 *

 * Returns:

 * - 0:   The maximum overall throughput capability is not indicated by

 *        the device separately and it must be determined from the per-slice

 *        max throughput (see @drm_dp_dsc_branch_slice_max_throughput())

 *        and the maximum slice count supported by the device.

 * - > 0: The maximum overall DSC pixel throughput supported by the branch

 *        device in kPixels/sec.

 */

int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],

					     bool is_rgb_yuv444)

{

	int throughput;



	if (is_rgb_yuv444)

		throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,

						 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0);

	else

		throughput = dsc_branch_dpcd_cap(dsc_branch_dpcd,

						 DP_DSC_BRANCH_OVERALL_THROUGHPUT_1);



	switch (throughput) {

	case 0:

		return 0;

	case 1:

		return 680000;

	default:

		return 600000 + 50000 * throughput;

	}

}

EXPORT_SYMBOL(drm_dp_dsc_branch_max_overall_throughput);



/**

 * drm_dp_dsc_branch_max_line_width() - Branch device's max DSC line width

 * @dsc_branch_dpcd: DSC branch capabilities from DPCD

 *

 * Return the branch device's maximum overall DSC line width, based on

 * the device's @dsc_branch_dpcd capabilities.

 *

 * Returns:

 * - 0:        The maximum line width is not indicated by the device

 *             separately and it must be determined from the maximum

 *             slice count and slice-width supported by the device.

 * - %-EINVAL: The device indicates an invalid maximum line width

 *             (< 5120 pixels).

 * - >= 5120:  The maximum line width in pixels.

 */

int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE])

{

	int line_width = dsc_branch_dpcd_cap(dsc_branch_dpcd, DP_DSC_BRANCH_MAX_LINE_WIDTH);



	switch (line_width) {

	case 0:

		return 0;

	case 1 ... 15:

		return -EINVAL;

	default:

		return line_width * 320;

	}

}

EXPORT_SYMBOL(drm_dp_dsc_branch_max_line_width);



static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,

				  const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,

				  u8 *buf, int buf_size)

drivers/gpu/drm/drm_atomic_uapi.c

+4 −0
Original line number Diff line number Diff line
@@ -419,6 +419,8 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, 
		set_out_fence_for_crtc(state->state, crtc, fence_ptr);

	} else if (property == crtc->scaling_filter_property) {

		state->scaling_filter = val;

	} else if (property == crtc->sharpness_strength_property) {

		state->sharpness_strength = val;

	} else if (crtc->funcs->atomic_set_property) {

		return crtc->funcs->atomic_set_property(crtc, state, property, val);

	} else {
@@ -456,6 +458,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, 
		*val = 0;

	else if (property == crtc->scaling_filter_property)

		*val = state->scaling_filter;

	else if (property == crtc->sharpness_strength_property)

		*val = state->sharpness_strength;

	else if (crtc->funcs->atomic_get_property)

		return crtc->funcs->atomic_get_property(crtc, state, property, val);

	else {

drivers/gpu/drm/drm_crtc.c

+35 −0
Original line number Diff line number Diff line
@@ -229,6 +229,25 @@ struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc) 
 * 		Driver's default scaling filter

 * 	Nearest Neighbor:

 * 		Nearest Neighbor scaling filter

 * SHARPNESS_STRENGTH:

 *	Atomic property for setting the sharpness strength/intensity by userspace.

 *

 *	The value of this property is set as an integer value ranging

 *	from 0 - 255 where:

 *

 *	0: Sharpness feature is disabled(default value).

 *

 *	1: Minimum sharpness.

 *

 *	255: Maximum sharpness.

 *

 *	User can gradually increase or decrease the sharpness level and can

 *	set the optimum value depending on content.

 *	This value will be passed to kernel through the UAPI.

 *	The setting of this property does not require modeset.

 *	The sharpness effect takes place post blending on the final composed output.

 *	If the feature is disabled, the content remains same without any sharpening effect

 *	and when this feature is applied, it enhances the clarity of the content.

 */



__printf(6, 0)
@@ -940,6 +959,22 @@ int drm_crtc_create_scaling_filter_property(struct drm_crtc *crtc, 
}

EXPORT_SYMBOL(drm_crtc_create_scaling_filter_property);



int drm_crtc_create_sharpness_strength_property(struct drm_crtc *crtc)

{

	struct drm_device *dev = crtc->dev;

	struct drm_property *prop =

		drm_property_create_range(dev, 0, "SHARPNESS_STRENGTH", 0, 255);



	if (!prop)

		return -ENOMEM;



	crtc->sharpness_strength_property = prop;

	drm_object_attach_property(&crtc->base, prop, 0);



	return 0;

}

EXPORT_SYMBOL(drm_crtc_create_sharpness_strength_property);



/**

 * drm_crtc_in_clone_mode - check if the given CRTC state is in clone mode

 *

drivers/gpu/drm/i915/Makefile

+12 −0
Original line number Diff line number Diff line
@@ -13,6 +13,11 @@ subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror 
# drivers. Define I915 when building i915.

subdir-ccflags-y += -DI915



# FIXME: Disable tracepoints on i915 for PREEMPT_RT, unfortunately

# it's an all or nothing flag. You cannot selectively disable

# only some tracepoints.

subdir-ccflags-$(CONFIG_PREEMPT_RT) += -DNOTRACE



subdir-ccflags-y += -I$(src)



# Please keep these build lists sorted!
@@ -26,6 +31,7 @@ i915-y += \ 
	i915_ioctl.o \

	i915_irq.o \

	i915_mitigations.o \

	i915_mmio_range.o \

	i915_module.o \

	i915_params.o \

	i915_pci.o \
@@ -228,6 +234,7 @@ i915-y += \ 
	display/intel_bios.o \

	display/intel_bo.o \

	display/intel_bw.o \

	display/intel_casf.o \

	display/intel_cdclk.o \

	display/intel_cmtg.o \

	display/intel_color.o \
@@ -236,6 +243,7 @@ i915-y += \ 
	display/intel_crtc.o \

	display/intel_crtc_state_dump.o \

	display/intel_cursor.o \

	display/intel_dbuf_bw.o \

	display/intel_display.o \

	display/intel_display_conversion.o \

	display/intel_display_driver.o \
@@ -248,6 +256,7 @@ i915-y += \ 
	display/intel_display_rpm.o \

	display/intel_display_rps.o \

	display/intel_display_snapshot.o \

	display/intel_display_utils.o \

	display/intel_display_wa.o \

	display/intel_dmc.o \

	display/intel_dmc_wl.o \
@@ -297,9 +306,11 @@ i915-y += \ 
	display/intel_vblank.o \

	display/intel_vga.o \

	display/intel_wm.o \

	display/skl_prefill.o \

	display/skl_scaler.o \

	display/skl_universal_plane.o \

	display/skl_watermark.o \

	display/vlv_clock.o \

	display/vlv_sideband.o

i915-$(CONFIG_ACPI) += \

	display/intel_acpi.o \
@@ -346,6 +357,7 @@ i915-y += \ 
	display/intel_gmbus.o \

	display/intel_hdmi.o \

	display/intel_lspcon.o \

	display/intel_lt_phy.o \

	display/intel_lvds.o \

	display/intel_panel.o \

	display/intel_pfit.o \

drivers/gpu/drm/i915/display/g4x_dp.c

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ 


#include "g4x_dp.h"

#include "i915_reg.h"

#include "i915_utils.h"

#include "intel_audio.h"

#include "intel_backlight.h"

#include "intel_connector.h"
@@ -20,6 +19,7 @@ 
#include "intel_display_power.h"

#include "intel_display_regs.h"

#include "intel_display_types.h"

#include "intel_display_utils.h"

#include "intel_dp.h"

#include "intel_dp_aux.h"

#include "intel_dp_link_training.h"