Commit 8f23a979 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/userq: integrate with enforce isolation 



Enforce isolation serializes access to the GFX IP.  User
queues are isolated in the MES scheduler, but we still
need to serialize between kernel queues and user queues.
For enforce isolation, group KGD user queues with KFD user
queues.

v2: split out variable renaming, add config guards
v3: use new function names

Reviewed-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 28fc3172

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+6 −0
Original line number Diff line number Diff line
@@ -1970,6 +1970,9 @@ static void amdgpu_gfx_kfd_sch_ctrl(struct amdgpu_device *adev, u32 idx, 
		if (adev->gfx.userq_sch_req_count[idx] == 0) {

			cancel_delayed_work_sync(&adev->gfx.enforce_isolation[idx].work);

			if (!adev->gfx.userq_sch_inactive[idx]) {

#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ

				amdgpu_userq_stop_sched_for_enforce_isolation(adev, idx);

#endif

				if (adev->kfd.init_complete)

					amdgpu_amdkfd_stop_sched(adev, idx);

				adev->gfx.userq_sch_inactive[idx] = true;
@@ -2027,6 +2030,9 @@ void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work) 
		/* Tell KFD to resume the runqueue */

		WARN_ON_ONCE(!adev->gfx.userq_sch_inactive[idx]);

		WARN_ON_ONCE(adev->gfx.userq_sch_req_count[idx]);

#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ

		amdgpu_userq_start_sched_for_enforce_isolation(adev, idx);

#endif

		if (adev->kfd.init_complete)

			amdgpu_amdkfd_start_sched(adev, idx);

		adev->gfx.userq_sch_inactive[idx] = false;