Commit 8f3589bb authored by JinZe.Xu's avatar JinZe.Xu Committed by Alex Deucher
Browse files

drm/amd/display: Restore rptr/wptr for DMCUB as workaround 



[Why]
States may be desync after resume.

[How]
Sync sw state with hw state.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarJinZe.Xu <JinZe.Xu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 278d3de6

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

+14 −0
Original line number Diff line number Diff line
@@ -340,6 +340,8 @@ struct dmub_srv_hw_funcs { 
	void (*setup_mailbox)(struct dmub_srv *dmub,

			      const struct dmub_region *inbox1);



	uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub);



	uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub);



	void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
@@ -600,6 +602,18 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 
 */

enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub);



/**

 * dmub_srv_sync_inbox1() - sync sw state with hw state

 * @dmub: the dmub service

 *

 * Sync sw state with hw state when resume from S0i3

 *

 * Return:

 *   DMUB_STATUS_OK - success

 *   DMUB_STATUS_INVALID - unspecified error

 */

enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub);



/**

 * dmub_srv_cmd_queue() - queues a command to the DMUB

 * @dmub: the dmub service

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

+5 −0
Original line number Diff line number Diff line
@@ -282,6 +282,11 @@ void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub, 
	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);

}



uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub)

{

	return REG_READ(DMCUB_INBOX1_WPTR);

}



uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)

{

	return REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

+2 −0
Original line number Diff line number Diff line
@@ -202,6 +202,8 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub, 
void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,

			      const struct dmub_region *inbox1);



uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub);



uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);



void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

+5 −0
Original line number Diff line number Diff line
@@ -242,6 +242,11 @@ void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub, 
	REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base);

}



uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub)

{

	return REG_READ(DMCUB_INBOX1_WPTR);

}



uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)

{

	return REG_READ(DMCUB_INBOX1_RPTR);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

+2 −0
Original line number Diff line number Diff line
@@ -204,6 +204,8 @@ void dmub_dcn31_setup_windows(struct dmub_srv *dmub, 
void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,

			      const struct dmub_region *inbox1);



uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub);



uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);



void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);