Commit 8f4de8f7 authored by Victor Lu's avatar Victor Lu Committed by Alex Deucher
Browse files

drm/amdgpu: Use correct SRIOV macro for gmc_v9_0_vm_fault_interrupt_state 



Under SRIOV, programming to VM_CONTEXT*_CNTL regs failed because the
current macro does not pass through the correct xcc instance.
Use the *REG32_XCC macro in this case.

The behaviour without SRIOV is the same without this patch.

Signed-off-by: default avatarVictor Lu <victorchengchi.lu@amd.com>
Reviewed-by: default avatarZhigang Luo <Zhigang.Luo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent bea07b21

drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

+4 −4
Original line number Diff line number Diff line
@@ -496,14 +496,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 
				if (j >= AMDGPU_MMHUB0(0))

					tmp = RREG32_SOC15_IP(MMHUB, reg);

				else

					tmp = RREG32_SOC15_IP(GC, reg);

					tmp = RREG32_XCC(reg, j);



				tmp &= ~bits;



				if (j >= AMDGPU_MMHUB0(0))

					WREG32_SOC15_IP(MMHUB, reg, tmp);

				else

					WREG32_SOC15_IP(GC, reg, tmp);

					WREG32_XCC(reg, tmp, j);

			}

		}

		break;
@@ -524,14 +524,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev, 
				if (j >= AMDGPU_MMHUB0(0))

					tmp = RREG32_SOC15_IP(MMHUB, reg);

				else

					tmp = RREG32_SOC15_IP(GC, reg);

					tmp = RREG32_XCC(reg, j);



				tmp |= bits;



				if (j >= AMDGPU_MMHUB0(0))

					WREG32_SOC15_IP(MMHUB, reg, tmp);

				else

					WREG32_SOC15_IP(GC, reg, tmp);

					WREG32_XCC(reg, tmp, j);

			}

		}

		break;