Commit 8fa9ca2e authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amd/display: Remove DCE12 guards 



Signed-off-by: default avatarJordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7fc6ff77

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+0 −2
Original line number Diff line number Diff line
@@ -1987,9 +1987,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) 
	case CHIP_POLARIS12:

	case CHIP_TONGA:

	case CHIP_FIJI:

#if defined(CONFIG_DRM_AMD_DC_DCE12_0)

	case CHIP_VEGA10:

#endif

#if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)

		return amdgpu_dc != 0;

#else

drivers/gpu/drm/amd/display/Kconfig

+0 −7
Original line number Diff line number Diff line
@@ -17,13 +17,6 @@ config DRM_AMD_DC_PRE_VEGA 
	  by default. This includes Polaris, Carrizo, Tonga, Bonaire,

	  and Hawaii.



config DRM_AMD_DC_DCE12_0

        bool "Vega10 family"

        depends on DRM_AMD_DC

        help

         Choose this option if you want to have

         VG family for display engine.



config DEBUG_KERNEL_DC

	bool "Enable kgdb break in DC"

	depends on DRM_AMD_DC

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+0 −4
Original line number Diff line number Diff line
@@ -1123,9 +1123,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
	case CHIP_POLARIS11:

	case CHIP_POLARIS10:

	case CHIP_POLARIS12:

#if defined(CONFIG_DRM_AMD_DC_DCE12_0)

	case CHIP_VEGA10:

#endif

		if (dce110_register_irq_handlers(dm->adev)) {

			DRM_ERROR("DM: Failed to initialize IRQ\n");

			return -1;
@@ -1392,13 +1390,11 @@ static int dm_early_init(void *handle) 
		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 6;

		break;

#if defined(CONFIG_DRM_AMD_DC_DCE12_0)

	case CHIP_VEGA10:

		adev->mode_info.num_crtc = 6;

		adev->mode_info.num_hpd = 6;

		adev->mode_info.num_dig = 6;

		break;

#endif

	default:

		DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type);

		return -EINVAL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c

+0 −2
Original line number Diff line number Diff line
@@ -402,7 +402,6 @@ bool dm_pp_notify_wm_clock_changes( 
	return false;

}



#if defined(CONFIG_DRM_AMD_DC_DCE12_0)

bool dm_pp_notify_wm_clock_changes_soc15(

	const struct dc_context *ctx,

	struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
@@ -410,7 +409,6 @@ bool dm_pp_notify_wm_clock_changes_soc15( 
	/* TODO: to be implemented */

	return false;

}

#endif



bool dm_pp_apply_power_level_change_request(

	const struct dc_context *ctx,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c

+0 −2
Original line number Diff line number Diff line
@@ -523,7 +523,6 @@ static void fill_plane_attributes_from_fb( 
	surface->tiling_info.gfx8.pipe_config =

			AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);



#if defined (CONFIG_DRM_AMD_DC_DCE12_0)

	if (adev->asic_type == CHIP_VEGA10) {

		/* Fill GFX9 params */

		surface->tiling_info.gfx9.num_pipes =
@@ -540,7 +539,6 @@ static void fill_plane_attributes_from_fb( 
			AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);

		surface->tiling_info.gfx9.shaderEnable = 1;

	}

#endif





	surface->plane_size.grph.surface_size.x = 0;