Commit 8fd6f64d authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Dmitry Baryshkov
Browse files

drm/msm/dsi: Remove dsi_phy_read/write() 



These are dummy wrappers that do literally nothing interesting.
Remove them.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/590700/
Link: https://lore.kernel.org/r/20240423-topic-msm_cleanup-v1-1-b30f39f43b90@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent ecbf9b3a

drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

+0 −2
Original line number Diff line number Diff line
@@ -12,8 +12,6 @@ 


#include "dsi.h"



#define dsi_phy_read(offset) readl((offset))

#define dsi_phy_write(offset, data) writel((data), (offset))

#define dsi_phy_write_udelay(offset, data, delay_us) { writel((data), (offset)); udelay(delay_us); }

#define dsi_phy_write_ndelay(offset, data, delay_ns) { writel((data), (offset)); ndelay(delay_ns); }

drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c

+121 −152

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drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c

+106 −109

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drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c

+54 −55
Original line number Diff line number Diff line
@@ -12,32 +12,32 @@ static void dsi_20nm_dphy_set_timing(struct msm_dsi_phy *phy, 
{

	void __iomem *base = phy->base;



	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0,

		DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1,

		DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2,

		DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));

	writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_0);

	writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_1);

	writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_2);

	if (timing->clk_zero & BIT(8))

		dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3,

			DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4,

		DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5,

		DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6,

		DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7,

		DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8,

		DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9,

		DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |

		DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10,

		DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));

	dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11,

		DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));

		writel(DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8,

		       base + REG_DSI_20nm_PHY_TIMING_CTRL_3);

	writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_4);

	writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_5);

	writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_6);

	writel(DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_7);

	writel(DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_8);

	writel(DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |

	       DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_9);

	writel(DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_10);

	writel(DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0),

	       base + REG_DSI_20nm_PHY_TIMING_CTRL_11);

}



static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
@@ -45,23 +45,23 @@ static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable) 
	void __iomem *base = phy->reg_base;



	if (!enable) {

		dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0);

		writel(0, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG);

		return;

	}



	if (phy->regulator_ldo_mode) {

		dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d);

		writel(0x1d, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL);

		return;

	}



	/* non LDO mode */

	dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03);

	dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03);

	dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00);

	dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20);

	dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01);

	dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00);

	dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03);

	writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1);

	writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2);

	writel(0x00, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3);

	writel(0x20, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4);

	writel(0x01, base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG);

	writel(0x00, phy->base + REG_DSI_20nm_PHY_LDO_CNTRL);

	writel(0x03, base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0);

}



static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy,
@@ -83,49 +83,48 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, 


	dsi_20nm_phy_regulator_ctrl(phy, true);



	dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);

	writel(0xff, base + REG_DSI_20nm_PHY_STRENGTH_0);



	val = dsi_phy_read(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);

	val = readl(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);

	if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_STANDALONE)

		val |= DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;

	else

		val &= ~DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL;

	dsi_phy_write(base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL, val);

	writel(val, base + REG_DSI_20nm_PHY_GLBL_TEST_CTRL);



	for (i = 0; i < 4; i++) {

		dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),

							(i >> 1) * 0x40);

		dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01);

		dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46);

		dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02);

		dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0);

		dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]);

		writel((i >> 1) * 0x40, base + REG_DSI_20nm_PHY_LN_CFG_3(i));

		writel(0x01, base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i));

		writel(0x46, base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i));

		writel(0x02, base + REG_DSI_20nm_PHY_LN_CFG_0(i));

		writel(0xa0, base + REG_DSI_20nm_PHY_LN_CFG_1(i));

		writel(cfg_4[i], base + REG_DSI_20nm_PHY_LN_CFG_4(i));

	}



	dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80);

	dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01);

	dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46);

	dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00);

	dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0);

	dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00);

	dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00);

	writel(0x80, base + REG_DSI_20nm_PHY_LNCK_CFG_3);

	writel(0x01, base + REG_DSI_20nm_PHY_LNCK_TEST_STR0);

	writel(0x46, base + REG_DSI_20nm_PHY_LNCK_TEST_STR1);

	writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_0);

	writel(0xa0, base + REG_DSI_20nm_PHY_LNCK_CFG_1);

	writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_2);

	writel(0x00, base + REG_DSI_20nm_PHY_LNCK_CFG_4);



	dsi_20nm_dphy_set_timing(phy, timing);



	dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00);

	writel(0x00, base + REG_DSI_20nm_PHY_CTRL_1);



	dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06);

	writel(0x06, base + REG_DSI_20nm_PHY_STRENGTH_1);



	/* make sure everything is written before enable */

	wmb();

	dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f);

	writel(0x7f, base + REG_DSI_20nm_PHY_CTRL_0);



	return 0;

}



static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)

{

	dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0);

	writel(0, phy->base + REG_DSI_20nm_PHY_CTRL_0);

	dsi_20nm_phy_regulator_ctrl(phy, false);

}

drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c

+110 −114

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