Commit 8ff3bb44 authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: add golden setting for gc v12 



Adding Manual GDB golden setting for gc v12
revision 0 ASIC.

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
(cherry picked from commit c9875d0a)
parent d507ae0d

drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c

+27 −0
Original line number Diff line number Diff line
@@ -202,6 +202,12 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { 
	SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ)

};



static const struct soc15_reg_golden golden_settings_gc_12_0[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),

	SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)

};



#define DEFAULT_SH_MEM_CONFIG \

	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \

	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
@@ -3432,6 +3438,24 @@ static void gfx_v12_0_disable_gpa_mode(struct amdgpu_device *adev) 
	WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);

}



static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev)

{

	if (amdgpu_sriov_vf(adev))

		return;



	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {

	case IP_VERSION(12, 0, 0):

	case IP_VERSION(12, 0, 1):

		if (adev->rev_id == 0)

			soc15_program_register_sequence(adev,

					golden_settings_gc_12_0,

					(const u32)ARRAY_SIZE(golden_settings_gc_12_0));

		break;

	default:

		break;

	}

}



static int gfx_v12_0_hw_init(void *handle)

{

	int r;
@@ -3472,6 +3496,9 @@ static int gfx_v12_0_hw_init(void *handle) 
		}

	}



	if (!amdgpu_emu_mode)

		gfx_v12_0_init_golden_registers(adev);



	adev->gfx.is_poweron = true;



	if (get_gb_addr_config(adev))