Commit 9040ecd0 authored by Nicolas Frattaroli's avatar Nicolas Frattaroli Committed by Yury Norov
Browse files

drm/rockchip: vop2: switch to FIELD_PREP_WM16 macro 



The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.

Remove VOP2's HIWORD_UPDATE macro from the vop2 header file, and replace
all instances in rockchip_vop2_reg.c (the only user of this particular
HIWORD_UPDATE definition) with equivalent FIELD_PREP_WM16 instances. This
gives us better error checking.

Reviewed-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tested-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Signed-off-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarYury Norov (NVIDIA) <yury.norov@gmail.com>
parent 1a99efa3

drivers/gpu/drm/rockchip/rockchip_drm_vop2.h

+0 −1
Original line number Diff line number Diff line
@@ -33,7 +33,6 @@ 
#define WIN_FEATURE_AFBDC		BIT(0)

#define WIN_FEATURE_CLUSTER		BIT(1)



#define HIWORD_UPDATE(v, h, l)  ((GENMASK(h, l) << 16) | ((v) << (l)))

/*

 *  the delay number of a window in different mode.

 */

drivers/gpu/drm/rockchip/rockchip_vop2_reg.c

+9 −6
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#include <linux/bitfield.h>

#include <linux/kernel.h>

#include <linux/component.h>

#include <linux/hw_bitfield.h>

#include <linux/mod_devicetable.h>

#include <linux/platform_device.h>

#include <linux/of.h>
@@ -1695,8 +1696,9 @@ static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 
		die |= RK3588_SYS_DSP_INFACE_EN_HDMI0 |

			    FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id);

		val = rk3588_get_hdmi_pol(polflags);

		regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 1, 1));

		regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 6, 5));

		regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(1), 1));

		regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0,

			     FIELD_PREP_WM16(GENMASK(6, 5), val));

		break;

	case ROCKCHIP_VOP2_EP_HDMI1:

		div &= ~RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV;
@@ -1707,8 +1709,9 @@ static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 
		die |= RK3588_SYS_DSP_INFACE_EN_HDMI1 |

			    FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id);

		val = rk3588_get_hdmi_pol(polflags);

		regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 4, 4));

		regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 8, 7));

		regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(4), 1));

		regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0,

			     FIELD_PREP_WM16(GENMASK(8, 7), val));

		break;

	case ROCKCHIP_VOP2_EP_EDP0:

		div &= ~RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV;
@@ -1718,7 +1721,7 @@ static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 
		die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX;

		die |= RK3588_SYS_DSP_INFACE_EN_EDP0 |

			   FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id);

		regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 0, 0));

		regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(0), 1));

		break;

	case ROCKCHIP_VOP2_EP_EDP1:

		div &= ~RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV;
@@ -1728,7 +1731,7 @@ static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 
		die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX;

		die |= RK3588_SYS_DSP_INFACE_EN_EDP1 |

			   FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id);

		regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 3, 3));

		regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, FIELD_PREP_WM16(BIT(3), 1));

		break;

	case ROCKCHIP_VOP2_EP_MIPI0:

		div &= ~RK3588_DSP_IF_MIPI0_PCLK_DIV;