Commit 90422219 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge patch series "Add SpacemiT K1 USB3.0 host controller support" 

Ze Huang <huang.ze@linux.dev> says:

The USB 3.0 controller found in the SpacemiT K1 SoC[1] supports both
USB3.0 Host and USB2.0 Dual-Role Device (DRD).

This controller is compatible with DesignWare Core USB 3 (DWC3) driver.
However, constraints in the `snps,dwc3` bindings limit the ability to
describe hardware-specific features in a clean and maintainable way.
While `dwc3-of-simple` still serves as a glue layer for many platforms,
it requires a split device tree node structure, which is less desirable
in newer platforms.

To promote a transition toward a flattened `dwc` node structure, this
series introduces `dwc3-generic-plat`, building upon prior efforts that
exposed the DWC3 core driver [2].

The device tree support for SpacemiT K1 will be submitted separately
when the associated PHY driver is ready.

Link: https://developer.spacemit.com/documentation?token=AjHDwrW78igAAEkiHracBI9HnTb [1]
Link: https://lore.kernel.org/all/20250414-dwc3-refactor-v7-3-f015b358722d@oss.qualcomm.com [2]
Link: https://lore.kernel.org/r/20250913-dwc3_generic-v8-0-b50f81f05f95@linux.dev


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parents a4d43c1f e0b6dc00

Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller



maintainers:

  - Ze Huang <huang.ze@linux.dev>



description: |

  The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions

  for USB 3.0 and DRD for USB 2.0.



  Key features:

  - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support

  - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)

  - Internal DMA controller and flexible endpoint FIFO sizing



  Communication Interface:

  - Use of PIPE3 (125MHz) interface for USB3.0 PHY

  - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY



allOf:

  - $ref: snps,dwc3-common.yaml#



properties:

  compatible:

    const: spacemit,k1-dwc3



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    const: usbdrd30



  interrupts:

    maxItems: 1



  phys:

    items:

      - description: phandle to USB2/HS PHY

      - description: phandle to USB3/SS PHY



  phy-names:

    items:

      - const: usb2-phy

      - const: usb3-phy



  resets:

    items:

      - description: USB3.0 AHB reset

      - description: USB3.0 VCC reset

      - description: USB3.0 PHY reset



  reset-names:

    items:

      - const: ahb

      - const: vcc

      - const: phy



  reset-delay:

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 2

    description: delay after reset sequence [us]



  vbus-supply:

    description: A phandle to the regulator supplying the VBUS voltage.



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - interrupts

  - phys

  - phy-names

  - resets

  - reset-names



unevaluatedProperties: false



examples:

  - |

    usb@c0a00000 {

        compatible = "spacemit,k1-dwc3";

        reg = <0xc0a00000 0x10000>;

        clocks = <&syscon_apmu 16>;

        clock-names = "usbdrd30";

        interrupts = <125>;

        phys = <&usb2phy>, <&usb3phy>;

        phy-names = "usb2-phy", "usb3-phy";

        resets = <&syscon_apmu 8>,

                 <&syscon_apmu 9>,

                 <&syscon_apmu 10>;

        reset-names = "ahb", "vcc", "phy";

        reset-delay = <2>;

        vbus-supply = <&usb3_vbus>;

        #address-cells = <1>;

        #size-cells = <0>;



        hub_2_0: hub@1 {

            compatible = "usb2109,2817";

            reg = <1>;

            vdd-supply = <&usb3_vhub>;

            peer-hub = <&hub_3_0>;

            reset-gpios = <&gpio 3 28 1>;

        };



        hub_3_0: hub@2 {

            compatible = "usb2109,817";

            reg = <2>;

            vdd-supply = <&usb3_vhub>;

            peer-hub = <&hub_2_0>;

            reset-gpios = <&gpio 3 28 1>;

        };

    };

drivers/usb/dwc3/Kconfig

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@@ -189,4 +189,15 @@ config USB_DWC3_RTK 
	  or dual-role mode.

	  Say 'Y' or 'M' if you have such device.



config USB_DWC3_GENERIC_PLAT

	tristate "DWC3 Generic Platform Driver"

	depends on OF && COMMON_CLK

	default USB_DWC3

	help

	  Support USB3 functionality in simple SoC integrations.

	  Currently supports SpacemiT DWC USB3. Platforms using

	  dwc3-of-simple can easily switch to dwc3-generic by flattening

	  the dwc3 child node in the device tree.

	  Say 'Y' or 'M' here if your platform integrates DWC3 in a similar way.



endif

drivers/usb/dwc3/Makefile

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@@ -57,3 +57,4 @@ obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o 
obj-$(CONFIG_USB_DWC3_XILINX)		+= dwc3-xilinx.o

obj-$(CONFIG_USB_DWC3_OCTEON)		+= dwc3-octeon.o

obj-$(CONFIG_USB_DWC3_RTK)		+= dwc3-rtk.o

obj-$(CONFIG_USB_DWC3_GENERIC_PLAT)	+= dwc3-generic-plat.o

drivers/usb/dwc3/dwc3-generic-plat.c

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// SPDX-License-Identifier: GPL-2.0-only

/*

 * dwc3-generic-plat.c - DesignWare USB3 generic platform driver

 *

 * Copyright (C) 2025 Ze Huang <huang.ze@linux.dev>

 *

 * Inspired by dwc3-qcom.c and dwc3-of-simple.c

 */



#include <linux/clk.h>

#include <linux/platform_device.h>

#include <linux/reset.h>

#include "glue.h"



struct dwc3_generic {

	struct device		*dev;

	struct dwc3		dwc;

	struct clk_bulk_data	*clks;

	int			num_clocks;

	struct reset_control	*resets;

};



#define to_dwc3_generic(d) container_of((d), struct dwc3_generic, dwc)



static void dwc3_generic_reset_control_assert(void *data)

{

	reset_control_assert(data);

}



static int dwc3_generic_probe(struct platform_device *pdev)

{

	struct dwc3_probe_data probe_data = {};

	struct device *dev = &pdev->dev;

	struct dwc3_generic *dwc3g;

	struct resource *res;

	int ret;



	dwc3g = devm_kzalloc(dev, sizeof(*dwc3g), GFP_KERNEL);

	if (!dwc3g)

		return -ENOMEM;



	dwc3g->dev = dev;



	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	if (!res) {

		dev_err(&pdev->dev, "missing memory resource\n");

		return -ENODEV;

	}



	dwc3g->resets = devm_reset_control_array_get_optional_exclusive(dev);

	if (IS_ERR(dwc3g->resets))

		return dev_err_probe(dev, PTR_ERR(dwc3g->resets), "failed to get resets\n");



	ret = reset_control_assert(dwc3g->resets);

	if (ret)

		return dev_err_probe(dev, ret, "failed to assert resets\n");



	/* Not strict timing, just for safety */

	udelay(2);



	ret = reset_control_deassert(dwc3g->resets);

	if (ret)

		return dev_err_probe(dev, ret, "failed to deassert resets\n");



	ret = devm_add_action_or_reset(dev, dwc3_generic_reset_control_assert, dwc3g->resets);

	if (ret)

		return ret;



	ret = devm_clk_bulk_get_all_enabled(dwc3g->dev, &dwc3g->clks);

	if (ret < 0)

		return dev_err_probe(dev, ret, "failed to get clocks\n");



	dwc3g->num_clocks = ret;

	dwc3g->dwc.dev = dev;

	probe_data.dwc = &dwc3g->dwc;

	probe_data.res = res;

	probe_data.ignore_clocks_and_resets = true;

	ret = dwc3_core_probe(&probe_data);

	if (ret)

		return dev_err_probe(dev, ret, "failed to register DWC3 Core\n");



	return 0;

}



static void dwc3_generic_remove(struct platform_device *pdev)

{

	struct dwc3 *dwc = platform_get_drvdata(pdev);

	struct dwc3_generic *dwc3g = to_dwc3_generic(dwc);



	dwc3_core_remove(dwc);



	clk_bulk_disable_unprepare(dwc3g->num_clocks, dwc3g->clks);

}



static int dwc3_generic_suspend(struct device *dev)

{

	struct dwc3 *dwc = dev_get_drvdata(dev);

	struct dwc3_generic *dwc3g = to_dwc3_generic(dwc);

	int ret;



	ret = dwc3_pm_suspend(dwc);

	if (ret)

		return ret;



	clk_bulk_disable_unprepare(dwc3g->num_clocks, dwc3g->clks);



	return 0;

}



static int dwc3_generic_resume(struct device *dev)

{

	struct dwc3 *dwc = dev_get_drvdata(dev);

	struct dwc3_generic *dwc3g = to_dwc3_generic(dwc);

	int ret;



	ret = clk_bulk_prepare_enable(dwc3g->num_clocks, dwc3g->clks);

	if (ret)

		return ret;



	ret = dwc3_pm_resume(dwc);

	if (ret)

		return ret;



	return 0;

}



static int dwc3_generic_runtime_suspend(struct device *dev)

{

	return dwc3_runtime_suspend(dev_get_drvdata(dev));

}



static int dwc3_generic_runtime_resume(struct device *dev)

{

	return dwc3_runtime_resume(dev_get_drvdata(dev));

}



static int dwc3_generic_runtime_idle(struct device *dev)

{

	return dwc3_runtime_idle(dev_get_drvdata(dev));

}



static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {

	SYSTEM_SLEEP_PM_OPS(dwc3_generic_suspend, dwc3_generic_resume)

	RUNTIME_PM_OPS(dwc3_generic_runtime_suspend, dwc3_generic_runtime_resume,

		       dwc3_generic_runtime_idle)

};



static const struct of_device_id dwc3_generic_of_match[] = {

	{ .compatible = "spacemit,k1-dwc3", },

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);



static struct platform_driver dwc3_generic_driver = {

	.probe		= dwc3_generic_probe,

	.remove		= dwc3_generic_remove,

	.driver		= {

		.name	= "dwc3-generic-plat",

		.of_match_table = dwc3_generic_of_match,

		.pm	= pm_ptr(&dwc3_generic_dev_pm_ops),

	},

};

module_platform_driver(dwc3_generic_driver);



MODULE_LICENSE("GPL");

MODULE_DESCRIPTION("DesignWare USB3 generic platform driver");