Commit 9073428b authored by Kim Phillips's avatar Kim Phillips Committed by Borislav Petkov (AMD)
Browse files

x86/sev: Allow IBPB-on-Entry feature for SNP guests 



The SEV-SNP IBPB-on-Entry feature does not require a guest-side
implementation. It was added in Zen5 h/w, after the first SNP Zen
implementation, and thus was not accounted for when the initial set of SNP
features were added to the kernel.

In its abundant precaution, commit

  8c29f016 ("x86/sev: Add SEV-SNP guest feature negotiation support")

included SEV_STATUS' IBPB-on-Entry bit as a reserved bit, thereby masking
guests from using the feature.

Allow guests to make use of IBPB-on-Entry when supported by the hypervisor, as
the bit is now architecturally defined and safe to expose.

Fixes: 8c29f016 ("x86/sev: Add SEV-SNP guest feature negotiation support")
Signed-off-by: default avatarKim Phillips <kim.phillips@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarNikunj A Dadhania <nikunj@amd.com>
Reviewed-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Cc: stable@kernel.org
Link: https://patch.msgid.link/20260203222405.4065706-2-kim.phillips@amd.com
parent 4ca191ce

arch/x86/boot/compressed/sev.c

+1 −0
Original line number Diff line number Diff line
@@ -188,6 +188,7 @@ bool sev_es_check_ghcb_fault(unsigned long address) 
				 MSR_AMD64_SNP_RESERVED_BIT13 |		\

				 MSR_AMD64_SNP_RESERVED_BIT15 |		\

				 MSR_AMD64_SNP_SECURE_AVIC |		\

				 MSR_AMD64_SNP_RESERVED_BITS19_22 |	\

				 MSR_AMD64_SNP_RESERVED_MASK)



#ifdef CONFIG_AMD_SECURE_AVIC

arch/x86/coco/sev/core.c

+1 −0
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ static const char * const sev_status_feat_names[] = { 
	[MSR_AMD64_SNP_VMSA_REG_PROT_BIT]	= "VMSARegProt",

	[MSR_AMD64_SNP_SMT_PROT_BIT]		= "SMTProt",

	[MSR_AMD64_SNP_SECURE_AVIC_BIT]		= "SecureAVIC",

	[MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT]	= "IBPBOnEntry",

};



/*

arch/x86/include/asm/msr-index.h

+4 −1
Original line number Diff line number Diff line
@@ -740,7 +740,10 @@ 
#define MSR_AMD64_SNP_SMT_PROT		BIT_ULL(MSR_AMD64_SNP_SMT_PROT_BIT)

#define MSR_AMD64_SNP_SECURE_AVIC_BIT	18

#define MSR_AMD64_SNP_SECURE_AVIC	BIT_ULL(MSR_AMD64_SNP_SECURE_AVIC_BIT)

#define MSR_AMD64_SNP_RESV_BIT		19

#define MSR_AMD64_SNP_RESERVED_BITS19_22 GENMASK_ULL(22, 19)

#define MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT	23

#define MSR_AMD64_SNP_IBPB_ON_ENTRY	BIT_ULL(MSR_AMD64_SNP_IBPB_ON_ENTRY_BIT)

#define MSR_AMD64_SNP_RESV_BIT		24

#define MSR_AMD64_SNP_RESERVED_MASK	GENMASK_ULL(63, MSR_AMD64_SNP_RESV_BIT)

#define MSR_AMD64_SAVIC_CONTROL		0xc0010138

#define MSR_AMD64_SAVIC_EN_BIT		0