Commit 9078e6c5 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Jakub Kicinski
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net: ravb: Make DBAT entry count configurable per-SoC 



Avoid wasting coherent DMA memory by allocating the descriptor base
address table sized for the actual number of DBAT/CDARq entries supported
by the SoC. Some platforms (for example GBETH) only provide two CDARq
entries; previously the driver always allocated space for 22 entries which
needlessly consumed memory on those systems.

Pass the per-SoC dbat_entry_num via struct ravb_hw_info and use it for
allocation and initialization in probe. This sizes the table correctly and
removes the unnecessary memory overhead on SoCs with fewer DBAT entries.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://patch.msgid.link/20251023112111.215198-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent c09b183d

drivers/net/ethernet/renesas/ravb.h

+1 −1
Original line number Diff line number Diff line
@@ -1017,7 +1017,6 @@ enum CSR2_BIT { 
#define CSR2_CSUM_ENABLE (CSR2_RTCP4 | CSR2_RUDP4 | CSR2_RICMP4 | \

			  CSR2_RTCP6 | CSR2_RUDP6 | CSR2_RICMP6)



#define DBAT_ENTRY_NUM	22

#define RX_QUEUE_OFFSET	4

#define NUM_RX_QUEUE	2

#define NUM_TX_QUEUE	2
@@ -1062,6 +1061,7 @@ struct ravb_hw_info { 
	u32 rx_max_frame_size;

	u32 rx_buffer_size;

	u32 rx_desc_size;

	u32 dbat_entry_num;

	unsigned aligned_tx: 1;

	unsigned coalesce_irqs:1;	/* Needs software IRQ coalescing */

drivers/net/ethernet/renesas/ravb_main.c

+7 −2
Original line number Diff line number Diff line
@@ -2714,6 +2714,7 @@ static const struct ravb_hw_info ravb_gen2_hw_info = { 
	.rx_buffer_size = SZ_2K +

			  SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),

	.rx_desc_size = sizeof(struct ravb_ex_rx_desc),

	.dbat_entry_num = 22,

	.aligned_tx = 1,

	.gptp = 1,

	.nc_queues = 1,
@@ -2737,6 +2738,7 @@ static const struct ravb_hw_info ravb_gen3_hw_info = { 
	.rx_buffer_size = SZ_2K +

			  SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),

	.rx_desc_size = sizeof(struct ravb_ex_rx_desc),

	.dbat_entry_num = 22,

	.internal_delay = 1,

	.tx_counters = 1,

	.multi_irqs = 1,
@@ -2763,6 +2765,7 @@ static const struct ravb_hw_info ravb_gen4_hw_info = { 
	.rx_buffer_size = SZ_2K +

			  SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),

	.rx_desc_size = sizeof(struct ravb_ex_rx_desc),

	.dbat_entry_num = 22,

	.internal_delay = 1,

	.tx_counters = 1,

	.multi_irqs = 1,
@@ -2789,6 +2792,7 @@ static const struct ravb_hw_info ravb_rzv2m_hw_info = { 
	.rx_buffer_size = SZ_2K +

			  SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),

	.rx_desc_size = sizeof(struct ravb_ex_rx_desc),

	.dbat_entry_num = 22,

	.multi_irqs = 1,

	.err_mgmt_irqs = 1,

	.gptp = 1,
@@ -2814,6 +2818,7 @@ static const struct ravb_hw_info gbeth_hw_info = { 
	.rx_max_frame_size = SZ_8K,

	.rx_buffer_size = SZ_2K,

	.rx_desc_size = sizeof(struct ravb_rx_desc),

	.dbat_entry_num = 2,

	.aligned_tx = 1,

	.coalesce_irqs = 1,

	.tx_counters = 1,
@@ -3045,7 +3050,7 @@ static int ravb_probe(struct platform_device *pdev) 
	ravb_parse_delay_mode(np, ndev);



	/* Allocate descriptor base address table */

	priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;

	priv->desc_bat_size = sizeof(struct ravb_desc) * info->dbat_entry_num;

	priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,

					    &priv->desc_bat_dma, GFP_KERNEL);

	if (!priv->desc_bat) {
@@ -3055,7 +3060,7 @@ static int ravb_probe(struct platform_device *pdev) 
		error = -ENOMEM;

		goto out_rpm_put;

	}

	for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)

	for (q = RAVB_BE; q < info->dbat_entry_num; q++)

		priv->desc_bat[q].die_dt = DT_EOS;



	/* Initialise HW timestamp list */