Commit 907fec2d authored by Victor Skvortsov's avatar Victor Skvortsov Committed by Alex Deucher
Browse files

drm/amdgpu: VF Query RAS Caps from Host if supported 



If VF RAS Capability support is enabled, guest is able to
retrieve the real RAS support from the host.

Signed-off-by: default avatarVictor Skvortsov <victor.skvortsov@amd.com>
Reviewed-by: default avatarZhigang Luo <zhigang.luo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9928509d

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+5 −0
Original line number Diff line number Diff line
@@ -3453,6 +3453,11 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) 
	if (!amdgpu_ras_asic_supported(adev))

		return;



	if (amdgpu_sriov_vf(adev)) {

		if (amdgpu_virt_get_ras_capability(adev))

			goto init_ras_enabled_flag;

	}



	/* query ras capability from psp */

	if (amdgpu_psp_get_ras_capability(&adev->psp))

		goto init_ras_enabled_flag;

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

+53 −0
Original line number Diff line number Diff line
@@ -523,6 +523,7 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) 


		adev->unique_id =

			((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid;

		adev->virt.ras_en_caps.all = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_en_caps.all;

		break;

	default:

		dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version);
@@ -1144,3 +1145,55 @@ bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) 


	return xnack_mode;

}



bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev)

{

	struct amdgpu_ras *con = amdgpu_ras_get_context(adev);



	if (!amdgpu_sriov_ras_caps_en(adev))

		return false;



	if (adev->virt.ras_en_caps.bits.block_umc)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__UMC);

	if (adev->virt.ras_en_caps.bits.block_sdma)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SDMA);

	if (adev->virt.ras_en_caps.bits.block_gfx)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__GFX);

	if (adev->virt.ras_en_caps.bits.block_mmhub)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MMHUB);

	if (adev->virt.ras_en_caps.bits.block_athub)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__ATHUB);

	if (adev->virt.ras_en_caps.bits.block_pcie_bif)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__PCIE_BIF);

	if (adev->virt.ras_en_caps.bits.block_hdp)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__HDP);

	if (adev->virt.ras_en_caps.bits.block_xgmi_wafl)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__XGMI_WAFL);

	if (adev->virt.ras_en_caps.bits.block_df)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__DF);

	if (adev->virt.ras_en_caps.bits.block_smn)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SMN);

	if (adev->virt.ras_en_caps.bits.block_sem)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SEM);

	if (adev->virt.ras_en_caps.bits.block_mp0)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP0);

	if (adev->virt.ras_en_caps.bits.block_mp1)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP1);

	if (adev->virt.ras_en_caps.bits.block_fuse)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__FUSE);

	if (adev->virt.ras_en_caps.bits.block_mca)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MCA);

	if (adev->virt.ras_en_caps.bits.block_vcn)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__VCN);

	if (adev->virt.ras_en_caps.bits.block_jpeg)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__JPEG);

	if (adev->virt.ras_en_caps.bits.block_ih)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__IH);

	if (adev->virt.ras_en_caps.bits.block_mpio)

		adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MPIO);



	if (adev->virt.ras_en_caps.bits.poison_propogation_mode)

		con->poison_supported = true; /* Poison is handled by host */



	return true;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

+7 −0
Original line number Diff line number Diff line
@@ -137,6 +137,7 @@ enum AMDGIM_FEATURE_FLAG { 
	AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7),

	/* MES info */

	AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8),

	AMDGIM_FEATURE_RAS_CAPS = (1 << 9),

};



enum AMDGIM_REG_ACCESS_FLAG {
@@ -277,6 +278,8 @@ struct amdgpu_virt { 
	uint32_t autoload_ucode_id;



	struct mutex rlcg_reg_lock;



	union amd_sriov_ras_caps ras_en_caps;

};



struct amdgpu_video_codec_info;
@@ -321,6 +324,9 @@ struct amdgpu_video_codec_info; 
#define amdgpu_sriov_vf_mmio_access_protection(adev) \

((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)



#define amdgpu_sriov_ras_caps_en(adev) \

((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS)



static inline bool is_virtual_machine(void)

{

#if defined(CONFIG_X86)
@@ -384,4 +390,5 @@ bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, 
					  u32 acc_flags, u32 hwip,

					  bool write, u32 *rlcg_flag);

u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);

bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev);

#endif