Unverified Commit 90986e35 authored by Lucas Stach's avatar Lucas Stach Committed by Robert Foss
Browse files

drm/bridge: analogix_dp: move macro reset after link bandwidth setting 



Setting the link bandwidth may change the PLL parameters, which will cause
the PLL to go out of lock, so make sure to apply the MACRO_RST, which
according to the comment is required to be pulsed after the PLL is locked.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarRobert Foss <rfoss@kernel.org>
Tested-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarRobert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240619182200.3752465-10-l.stach@pengutronix.de
parent b8a4cdbb

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

+10 −8
Original line number Diff line number Diff line
@@ -243,6 +243,11 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp) 


	/* Set link rate and count as you want to establish*/

	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);

	/*

	 * MACRO_RST must be applied after the PLL_LOCK to avoid

	 * the DP inter pair skew issue for at least 10 us

	 */

	analogix_dp_reset_macro(dp);

	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);



	/* Setup RX configuration */
@@ -562,12 +567,6 @@ static int analogix_dp_full_link_train(struct analogix_dp_device *dp, 
	int retval = 0;

	bool training_finished = false;



	/*

	 * MACRO_RST must be applied after the PLL_LOCK to avoid

	 * the DP inter pair skew issue for at least 10 us

	 */

	analogix_dp_reset_macro(dp);



	/* Initialize by reading RX's DPCD */

	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);

	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
@@ -634,9 +633,12 @@ static int analogix_dp_fast_link_train(struct analogix_dp_device *dp) 
	u8 link_align, link_status[2];

	enum pll_status status;



	analogix_dp_reset_macro(dp);



	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);

	/*

	 * MACRO_RST must be applied after the PLL_LOCK to avoid

	 * the DP inter pair skew issue for at least 10 us

	 */

	analogix_dp_reset_macro(dp);

	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);

	analogix_dp_set_lane_link_training(dp);