Commit 90a498f2 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy updates from Vinod Koul:
 "New hardware support:

   - Qualcomm X1E80100 PCIe phy support, SM8550 PCIe1 PHY, SC7180 UFS
     PHY and SDM630 USBC support

   - Rockchip HDMI/eDP Combo PHY driver

   - Mediatek MT8365 CSI phy driver

  Updates:

   - Rework on Qualcomm phy PCS registers and type-c handling

   - Cadence torrent phy updates for multilink configuration

   - TI gmii resume support"

* tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits)
  phy: constify of_phandle_args in xlate
  phy: ti: tusb1210: Define device IDs
  phy: ti: tusb1210: Use temporary variable for struct device
  phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver
  dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema
  phy: ti: gmii-sel: add resume support
  phy: mtk-mipi-csi: add driver for CSI phy
  dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
  phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config for TI J7200
  dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200
  phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink configuration
  phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration
  dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1
  phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API
  dt-bindings: phy: qmp-ufs: Fix PHY clocks
  phy: qcom: sgmii-eth: move PCS registers to separate header
  phy: qcom: sgmii-eth: use existing register definitions
  phy: qcom: qmp-usbc: drop has_pwrdn_delay handling
  phy: qcom: qmp: move common bits definitions to common header
  phy: qcom: qmp: split DP PHY registers to separate headers
  ...
parents 4438a810 00ca8a15

Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml

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+79 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (c) 2023 MediaTek, BayLibre

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mediatek Sensor Interface MIPI CSI CD-PHY



maintainers:

  - Julien Stephan <jstephan@baylibre.com>

  - Andy Hsieh <andy.hsieh@mediatek.com>



description:

  The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2

  receivers. The number of PHYs depends on the SoC model.

  Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only

  capable.



properties:

  compatible:

    enum:

      - mediatek,mt8365-csi-rx



  reg:

    maxItems: 1



  num-lanes:

    enum: [2, 3, 4]



  '#phy-cells':

    enum: [0, 1]

    description: |

      If the PHY doesn't support mode selection then #phy-cells must be 0 and

      PHY mode is described using phy-type property.

      If the PHY supports mode selection, then #phy-cells must be 1 and mode

      is set in the PHY cells. Supported modes are:

        - PHY_TYPE_DPHY

        - PHY_TYPE_CPHY

      See include/dt-bindings/phy/phy.h for constants.



  phy-type:

    description:

      If the PHY doesn't support mode selection then this set the operating mode.

      See include/dt-bindings/phy/phy.h for constants.

    const: 10

    $ref: /schemas/types.yaml#/definitions/uint32



required:

  - compatible

  - reg

  - num-lanes

  - '#phy-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/phy/phy.h>

    soc {

      #address-cells = <2>;

      #size-cells = <2>;



      csi0_rx: phy@11c10000 {

        compatible = "mediatek,mt8365-csi-rx";

        reg = <0 0x11c10000 0 0x2000>;

        num-lanes = <2>;

        #phy-cells = <1>;

      };



      csi1_rx: phy@11c12000 {

        compatible = "mediatek,mt8365-csi-rx";

        reg = <0 0x11c12000 0 0x2000>;

        phy-type = <PHY_TYPE_DPHY>;

        num-lanes = <2>;

        #phy-cells = <0>;

      };

    };

...

Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml

+8 −3
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ properties: 
  compatible:

    enum:

      - cdns,torrent-phy

      - ti,j7200-serdes-10g

      - ti,j721e-serdes-10g



  '#address-cells':
@@ -35,14 +36,18 @@ properties: 
    minItems: 1

    maxItems: 2

    description:

      PHY reference clock for 1 item. Must contain an entry in clock-names.

      Optional Parent to enable output reference clock.

      PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).

      pll1_refclk is optional and used for multi-protocol configurations requiring

      separate reference clock for each protocol.

      Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.

      Optional parent clock (phy_en_refclk) to enable a reference clock output feature

      on some platforms to output either derived or received reference clock.



  clock-names:

    minItems: 1

    items:

      - const: refclk

      - const: phy_en_refclk

      - enum: [ pll1_refclk, phy_en_refclk ]



  reg:

    minItems: 1

Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm QMP PHY controller (USB, MSM8998)



maintainers:

  - Vinod Koul <vkoul@kernel.org>



description:

  The QMP PHY controller supports physical layer functionality for USB-C on

  several Qualcomm chipsets.



properties:

  compatible:

    enum:

      - qcom,msm8998-qmp-usb3-phy

      - qcom,qcm2290-qmp-usb3-phy

      - qcom,sdm660-qmp-usb3-phy

      - qcom,sm6115-qmp-usb3-phy



  reg:

    maxItems: 1



  clocks:

    maxItems: 4



  clock-names:

    maxItems: 4



  resets:

    maxItems: 2



  reset-names:

    items:

      - const: phy

      - const: phy_phy



  vdda-phy-supply: true



  vdda-pll-supply: true



  "#clock-cells":

    const: 0



  clock-output-names:

    maxItems: 1



  "#phy-cells":

    const: 0



  orientation-switch:

    description:

      Flag the PHY as possible handler of USB Type-C orientation switching

    type: boolean



  qcom,tcsr-reg:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: phandle to TCSR hardware block

          - description: offset of the VLS CLAMP register

    description: Clamp register present in the TCSR



  ports:

    $ref: /schemas/graph.yaml#/properties/ports

    properties:

      port@0:

        $ref: /schemas/graph.yaml#/properties/port

        description: Output endpoint of the PHY



      port@1:

        $ref: /schemas/graph.yaml#/properties/port

        description: Incoming endpoint from the USB controller



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - resets

  - reset-names

  - vdda-phy-supply

  - vdda-pll-supply

  - "#clock-cells"

  - clock-output-names

  - "#phy-cells"

  - qcom,tcsr-reg



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8998-qmp-usb3-phy

              - qcom,sdm660-qmp-usb3-phy

    then:

      properties:

        clocks:

          maxItems: 4

        clock-names:

          items:

            - const: aux

            - const: ref

            - const: cfg_ahb

            - const: pipe



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,qcm2290-qmp-usb3-phy

              - qcom,sm6115-qmp-usb3-phy

    then:

      properties:

        clocks:

          maxItems: 4

        clock-names:

          items:

            - const: cfg_ahb

            - const: ref

            - const: com_aux

            - const: pipe



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-msm8998.h>

    #include <dt-bindings/clock/qcom,rpmh.h>



    phy@c010000 {

      compatible = "qcom,msm8998-qmp-usb3-phy";

      reg = <0x0c010000 0x1000>;



      clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,

               <&gcc GCC_USB3_CLKREF_CLK>,

               <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

               <&gcc GCC_USB3_PHY_PIPE_CLK>;

      clock-names = "aux",

                    "ref",

                    "cfg_ahb",

                    "pipe";

      clock-output-names = "usb3_phy_pipe_clk_src";

      #clock-cells = <0>;

      #phy-cells = <0>;



      resets = <&gcc GCC_USB3_PHY_BCR>,

               <&gcc GCC_USB3PHY_PHY_BCR>;

      reset-names = "phy",

                    "phy_phy";



      vdda-phy-supply = <&vreg_l1a_0p875>;

      vdda-pll-supply = <&vreg_l2a_1p2>;



      orientation-switch;



      qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>;



      ports {

        #address-cells = <1>;

        #size-cells = <0>;



        port@0 {

          reg = <0>;



          endpoint {

            remote-endpoint = <&pmic_typec_mux_in>;

          };

        };



        port@1 {

          reg = <1>;



          endpoint {

            remote-endpoint = <&usb_dwc3_ss>;

          };

        };

      };

    };

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

+6 −0
Original line number Diff line number Diff line
@@ -38,6 +38,8 @@ properties: 
      - qcom,sm8550-qmp-gen4x2-pcie-phy

      - qcom,sm8650-qmp-gen3x2-pcie-phy

      - qcom,sm8650-qmp-gen4x2-pcie-phy

      - qcom,x1e80100-qmp-gen3x2-pcie-phy

      - qcom,x1e80100-qmp-gen4x2-pcie-phy



  reg:

    minItems: 1
@@ -151,6 +153,8 @@ allOf: 
              - qcom,sm8550-qmp-gen4x2-pcie-phy

              - qcom,sm8650-qmp-gen3x2-pcie-phy

              - qcom,sm8650-qmp-gen4x2-pcie-phy

              - qcom,x1e80100-qmp-gen3x2-pcie-phy

              - qcom,x1e80100-qmp-gen4x2-pcie-phy

    then:

      properties:

        clocks:
@@ -194,6 +198,8 @@ allOf: 
            enum:

              - qcom,sm8550-qmp-gen4x2-pcie-phy

              - qcom,sm8650-qmp-gen4x2-pcie-phy

              - qcom,x1e80100-qmp-gen3x2-pcie-phy

              - qcom,x1e80100-qmp-gen4x2-pcie-phy

    then:

      properties:

        resets:

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml

+22 −26
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ properties: 
      - qcom,msm8996-qmp-ufs-phy

      - qcom,msm8998-qmp-ufs-phy

      - qcom,sa8775p-qmp-ufs-phy

      - qcom,sc7180-qmp-ufs-phy

      - qcom,sc7280-qmp-ufs-phy

      - qcom,sc8180x-qmp-ufs-phy

      - qcom,sc8280xp-qmp-ufs-phy
@@ -38,15 +39,12 @@ properties: 
    maxItems: 1



  clocks:

    minItems: 1

    minItems: 2

    maxItems: 3



  clock-names:

    minItems: 1

    items:

      - const: ref

      - const: ref_aux

      - const: qref

    minItems: 2

    maxItems: 3



  power-domains:

    maxItems: 1
@@ -86,22 +84,9 @@ allOf: 
        compatible:

          contains:

            enum:

              - qcom,msm8998-qmp-ufs-phy

              - qcom,sa8775p-qmp-ufs-phy

              - qcom,sc7280-qmp-ufs-phy

              - qcom,sm8450-qmp-ufs-phy

    then:

      properties:

        clocks:

          minItems: 3

        clock-names:

          minItems: 3



  - if:

      properties:

        compatible:

          contains:

            enum:

              - qcom,msm8998-qmp-ufs-phy

              - qcom,sc8180x-qmp-ufs-phy

              - qcom,sc8280xp-qmp-ufs-phy

              - qcom,sdm845-qmp-ufs-phy
@@ -112,14 +97,19 @@ allOf: 
              - qcom,sm8150-qmp-ufs-phy

              - qcom,sm8250-qmp-ufs-phy

              - qcom,sm8350-qmp-ufs-phy

              - qcom,sm8450-qmp-ufs-phy

              - qcom,sm8550-qmp-ufs-phy

              - qcom,sm8650-qmp-ufs-phy

    then:

      properties:

        clocks:

          maxItems: 2

          minItems: 3

          maxItems: 3

        clock-names:

          maxItems: 2

          items:

            - const: ref

            - const: ref_aux

            - const: qref



  - if:

      properties:
@@ -130,22 +120,28 @@ allOf: 
    then:

      properties:

        clocks:

          maxItems: 1

          minItems: 2

          maxItems: 2

        clock-names:

          maxItems: 1

          items:

            - const: ref

            - const: qref



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

    #include <dt-bindings/clock/qcom,rpmh.h>



    ufs_mem_phy: phy@1d87000 {

        compatible = "qcom,sc8280xp-qmp-ufs-phy";

        reg = <0x01d87000 0x1000>;



        clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

        clock-names = "ref", "ref_aux";

        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,

                 <&gcc GCC_UFS_REF_CLKREF_CLK>;



        clock-names = "ref", "ref_aux", "qref";



        power-domains = <&gcc UFS_PHY_GDSC>;