Commit 90c64cc0 authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Vinod Koul
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phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoC 



UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the
required register settings using the tables_hs_g4 struct instance.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-11-manivannan.sadhasivam@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 0d46b98d

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+36 −0
Original line number Diff line number Diff line
@@ -576,6 +576,34 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { 
	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

};



static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),

};



static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),

	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),

};



static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),

};



struct qmp_ufs_offsets {

	u16 serdes;

	u16 pcs;
@@ -882,6 +910,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { 
		.serdes		= sm8350_ufsphy_hs_b_serdes,

		.serdes_num	= ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),

	},

	.tbls_hs_g4 = {

		.tx		= sm8350_ufsphy_g4_tx,

		.tx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_tx),

		.rx		= sm8350_ufsphy_g4_rx,

		.rx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_rx),

		.pcs		= sm8350_ufsphy_g4_pcs,

		.pcs_num	= ARRAY_SIZE(sm8350_ufsphy_g4_pcs),

	},

	.clk_list		= sdm845_ufs_phy_clk_l,

	.num_clks		= ARRAY_SIZE(sdm845_ufs_phy_clk_l),

	.vreg_list		= qmp_phy_vreg_l,