Unverified Commit 90ed6887 authored by Alexander Stein's avatar Alexander Stein Committed by Mark Brown
Browse files

ASoC: fsl_sai: Add missing registers to cache default 



Drivers does cache sync during runtime resume, setting all writable
registers. Not all writable registers are set in cache default, resulting
in the erorr message:
  fsl-sai 30c30000.sai: using zero-initialized flat cache, this may cause
  unexpected behavior

Fix this by adding missing writable register defaults.

Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Link: https://patch.msgid.link/20251216102246.676181-1-alexander.stein@ew.tq-group.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 00b960a8

sound/soc/fsl/fsl_sai.c

+3 −0
Original line number Diff line number Diff line
@@ -1081,6 +1081,7 @@ static const struct reg_default fsl_sai_reg_defaults_ofs0[] = { 
	{FSL_SAI_TDR6, 0},

	{FSL_SAI_TDR7, 0},

	{FSL_SAI_TMR, 0},

	{FSL_SAI_TTCTL, 0},

	{FSL_SAI_RCR1(0), 0},

	{FSL_SAI_RCR2(0), 0},

	{FSL_SAI_RCR3(0), 0},
@@ -1104,12 +1105,14 @@ static const struct reg_default fsl_sai_reg_defaults_ofs8[] = { 
	{FSL_SAI_TDR6, 0},

	{FSL_SAI_TDR7, 0},

	{FSL_SAI_TMR, 0},

	{FSL_SAI_TTCTL, 0},

	{FSL_SAI_RCR1(8), 0},

	{FSL_SAI_RCR2(8), 0},

	{FSL_SAI_RCR3(8), 0},

	{FSL_SAI_RCR4(8), 0},

	{FSL_SAI_RCR5(8), 0},

	{FSL_SAI_RMR, 0},

	{FSL_SAI_RTCTL, 0},

	{FSL_SAI_MCTL, 0},

	{FSL_SAI_MDIV, 0},

};