Commit 9149c9b0 authored by Faisal Hassan's avatar Faisal Hassan Committed by Greg Kroah-Hartman
Browse files

usb: dwc3: core: update LC timer as per USB Spec V3.2 



This fix addresses STAR 9001285599, which only affects DWC_usb3 version
3.20a. The timer value for PM_LC_TIMER in DWC_usb3 3.20a for the Link
ECN changes is incorrect. If the PM TIMER ECN is enabled via GUCTL2[19],
the link compliance test (TD7.21) may fail. If the ECN is not enabled
(GUCTL2[19] = 0), the controller will use the old timer value (5us),
which is still acceptable for the link compliance test. Therefore, clear
GUCTL2[19] to pass the USB link compliance test: TD 7.21.

Cc: stable@vger.kernel.org
Signed-off-by: default avatarFaisal Hassan <quic_faisalh@quicinc.com>
Acked-by: default avatarThinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/20240829094502.26502-1-quic_faisalh@quicinc.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 00dcf2fa

drivers/usb/dwc3/core.c

+15 −0
Original line number Diff line number Diff line
@@ -1386,6 +1386,21 @@ static int dwc3_core_init(struct dwc3 *dwc) 
		dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);

	}



	/*

	 * STAR 9001285599: This issue affects DWC_usb3 version 3.20a

	 * only. If the PM TIMER ECM is enabled through GUCTL2[19], the

	 * link compliance test (TD7.21) may fail. If the ECN is not

	 * enabled (GUCTL2[19] = 0), the controller will use the old timer

	 * value (5us), which is still acceptable for the link compliance

	 * test. Therefore, do not enable PM TIMER ECM in 3.20a by

	 * setting GUCTL2[19] by default; instead, use GUCTL2[19] = 0.

	 */

	if (DWC3_VER_IS(DWC3, 320A)) {

		reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);

		reg &= ~DWC3_GUCTL2_LC_TIMER;

		dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);

	}



	/*

	 * When configured in HOST mode, after issuing U3/L2 exit controller

	 * fails to send proper CRC checksum in CRC5 feild. Because of this

drivers/usb/dwc3/core.h

+2 −0
Original line number Diff line number Diff line
@@ -421,6 +421,7 @@ 


/* Global User Control Register 2 */

#define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)

#define DWC3_GUCTL2_LC_TIMER			BIT(19)



/* Global User Control Register 3 */

#define DWC3_GUCTL3_SPLITDISABLE		BIT(14)
@@ -1269,6 +1270,7 @@ struct dwc3 { 
#define DWC3_REVISION_290A	0x5533290a

#define DWC3_REVISION_300A	0x5533300a

#define DWC3_REVISION_310A	0x5533310a

#define DWC3_REVISION_320A	0x5533320a

#define DWC3_REVISION_330A	0x5533330a



#define DWC31_REVISION_ANY	0x0