Unverified Commit 914e618b authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "Add support for a few Zc* extensions, Zcmop and Zimop" 

Clément Léger <cleger@rivosinc.com> says:

Add support for (yet again) more RVA23U64 missing extensions. Add
support for Zimop, Zcmop, Zca, Zcf, Zcd and Zcb extensions ISA string
parsing, hwprobe and kvm support. Zce, Zcmt and Zcmp extensions have
been left out since they target microcontrollers/embedded CPUs and are
not needed by RVA23U64.

Since Zc* extensions states that C implies Zca, Zcf (if F and RV32), Zcd
(if D), this series modifies the way ISA string is parsed and now does
it in two phases. First one parses the string and the second one
validates it for the final ISA description.

* b4-shazam-merge:
  KVM: riscv: selftests: Add Zcmop extension to get-reg-list test
  RISC-V: KVM: Allow Zcmop extension for Guest/VM
  riscv: hwprobe: export Zcmop ISA extension
  riscv: add ISA extension parsing for Zcmop
  dt-bindings: riscv: add Zcmop ISA extension description
  KVM: riscv: selftests: Add some Zc* extensions to get-reg-list test
  RISC-V: KVM: Allow Zca, Zcf, Zcd and Zcb extensions for Guest/VM
  riscv: hwprobe: export Zca, Zcf, Zcd and Zcb ISA extensions
  riscv: add ISA parsing for Zca, Zcf, Zcd and Zcb
  riscv: add ISA extensions validation callback
  dt-bindings: riscv: add Zca, Zcf, Zcd and Zcb ISA extension description
  KVM: riscv: selftests: Add Zimop extension to get-reg-list test
  RISC-V: KVM: Allow Zimop extension for Guest/VM
  riscv: hwprobe: export Zimop ISA extension
  riscv: add ISA extension parsing for Zimop
  dt-bindings: riscv: add Zimop ISA extension description

Link: https://lore.kernel.org/r/20240619113529.676940-1-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents d4b539ad e212d92d

Documentation/arch/riscv/hwprobe.rst

+28 −0
Original line number Diff line number Diff line
@@ -207,6 +207,34 @@ The following keys are defined: 
  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is

       supported as defined in the RISC-V ISA manual starting from commit

       58220614a5f ("Zimop is ratified/1.0").



  * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard

       extensions for code size reduction, as ratified in commit 8be3419c1c0

       ("Zcf doesn't exist on RV64 as it contains no instructions") of

       riscv-code-size-reduction.



  * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard

       extensions for code size reduction, as ratified in commit 8be3419c1c0

       ("Zcf doesn't exist on RV64 as it contains no instructions") of

       riscv-code-size-reduction.



  * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard

       extensions for code size reduction, as ratified in commit 8be3419c1c0

       ("Zcf doesn't exist on RV64 as it contains no instructions") of

       riscv-code-size-reduction.



  * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard

       extensions for code size reduction, as ratified in commit 8be3419c1c0

       ("Zcf doesn't exist on RV64 as it contains no instructions") of

       riscv-code-size-reduction.



  * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is

       supported as defined in the RISC-V ISA manual starting from commit

       c732a4f39a4 ("Zcmop is ratified/1.0").



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

Documentation/devicetree/bindings/riscv/extensions.yaml

+95 −0
Original line number Diff line number Diff line
@@ -220,6 +220,43 @@ properties: 
            instructions as ratified at commit 6d33919 ("Merge pull request #158

            from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.



        - const: zca

          description: |

            The Zca extension part of Zc* standard extensions for code size

            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on

            RV64 as it contains no instructions") of riscv-code-size-reduction,

            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed

            of zc.adoc to src tree.").



        - const: zcb

          description: |

            The Zcb extension part of Zc* standard extensions for code size

            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on

            RV64 as it contains no instructions") of riscv-code-size-reduction,

            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed

            of zc.adoc to src tree.").



        - const: zcd

          description: |

            The Zcd extension part of Zc* standard extensions for code size

            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on

            RV64 as it contains no instructions") of riscv-code-size-reduction,

            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed

            of zc.adoc to src tree.").



        - const: zcf

          description: |

            The Zcf extension part of Zc* standard extensions for code size

            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on

            RV64 as it contains no instructions") of riscv-code-size-reduction,

            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed

            of zc.adoc to src tree.").



        - const: zcmop

          description:

            The standard Zcmop extension version 1.0, as ratified in commit

            c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.



        - const: zfa

          description:

            The standard Zfa extension for additional floating point
@@ -363,6 +400,11 @@ properties: 
            ratified in the 20191213 version of the unprivileged ISA

            specification.



        - const: zimop

          description:

            The standard Zimop extension version 1.0, as ratified in commit

            58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.



        - const: ztso

          description:

            The standard Ztso extension for total store ordering, as ratified
@@ -514,5 +556,58 @@ properties: 
            Registers in the AX45MP datasheet.

            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf



    allOf:

      # Zcb depends on Zca

      - if:

          contains:

            const: zcb

        then:

          contains:

            const: zca

      # Zcd depends on Zca and D

      - if:

          contains:

            const: zcd

        then:

          allOf:

            - contains:

                const: zca

            - contains:

                const: d

      # Zcf depends on Zca and F

      - if:

          contains:

            const: zcf

        then:

          allOf:

            - contains:

                const: zca

            - contains:

                const: f

      # Zcmop depends on Zca

      - if:

          contains:

            const: zcmop

        then:

          contains:

            const: zca



allOf:

  # Zcf extension does not exist on rv64

  - if:

      properties:

        riscv,isa-extensions:

          contains:

            const: zcf

        riscv,isa-base:

          contains:

            const: rv64i

    then:

      properties:

        riscv,isa-extensions:

          not:

            contains:

              const: zcf



additionalProperties: true

...

arch/riscv/include/asm/cpufeature.h

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ struct riscv_isa_ext_data { 
	const char *property;

	const unsigned int *subset_ext_ids;

	const unsigned int subset_ext_size;

	int (*validate)(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap);

};



extern const struct riscv_isa_ext_data riscv_isa_ext[];

arch/riscv/include/asm/hwcap.h

+6 −0
Original line number Diff line number Diff line
@@ -86,6 +86,12 @@ 
#define RISCV_ISA_EXT_ZVE64X		77

#define RISCV_ISA_EXT_ZVE64F		78

#define RISCV_ISA_EXT_ZVE64D		79

#define RISCV_ISA_EXT_ZIMOP		80

#define RISCV_ISA_EXT_ZCA		81

#define RISCV_ISA_EXT_ZCB		82

#define RISCV_ISA_EXT_ZCD		83

#define RISCV_ISA_EXT_ZCF		84

#define RISCV_ISA_EXT_ZCMOP		85



#define RISCV_ISA_EXT_XLINUXENVCFG	127

arch/riscv/include/uapi/asm/hwprobe.h

+6 −0
Original line number Diff line number Diff line
@@ -65,6 +65,12 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 39)

#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 40)

#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 41)

#define		RISCV_HWPROBE_EXT_ZIMOP		(1ULL << 42)

#define		RISCV_HWPROBE_EXT_ZCA		(1ULL << 43)

#define		RISCV_HWPROBE_EXT_ZCB		(1ULL << 44)

#define		RISCV_HWPROBE_EXT_ZCD		(1ULL << 45)

#define		RISCV_HWPROBE_EXT_ZCF		(1ULL << 46)

#define		RISCV_HWPROBE_EXT_ZCMOP		(1ULL << 47)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)