Commit 918d7795 authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Thomas Bogendoerfer
Browse files

MIPS: Octeon: Opt-out 4k_cache feature 



Octeon has a different cache interface with traditional R4K one,
just opt-out this flag for octeon to avoid run R4K cache initialization
code accidentally.

Also remove ISA level assumption for 4k cache.

Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent e1aa1dfe

arch/mips/include/asm/cpu-features.h

+1 −1
Original line number Diff line number Diff line
@@ -118,7 +118,7 @@ 
#define cpu_has_3k_cache	__isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)

#endif

#ifndef cpu_has_4k_cache

#define cpu_has_4k_cache	__isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)

#define cpu_has_4k_cache	__opt(MIPS_CPU_4K_CACHE)

#endif

#ifndef cpu_has_octeon_cache

#define cpu_has_octeon_cache	0

arch/mips/kernel/cpu-probe.c

+2 −0
Original line number Diff line number Diff line
@@ -1602,6 +1602,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 
static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)

{

	decode_configs(c);

	/* Octeon has different cache interface */

	c->options &= ~MIPS_CPU_4K_CACHE;

	switch (c->processor_id & PRID_IMP_MASK) {

	case PRID_IMP_CAVIUM_CN38XX:

	case PRID_IMP_CAVIUM_CN31XX: