spi: Use inclusive language

#include "internals.h"

static DEFINE_IDR(spi_master_idr);

static DEFINE_IDR(spi_controller_idr);

static void spidev_release(struct device *dev)

{

	.attrs  = spi_controller_statistics_attrs,

};

static const struct attribute_group *spi_master_groups[] = {

static const struct attribute_group *spi_controller_groups[] = {

	&spi_controller_statistics_group,

	NULL,

};

					spi_toggle_csgpiod(spi, idx, enable, activate);

			}

		}

		/* Some SPI masters need both GPIO CS & slave_select */

		/* Some SPI controllers need both GPIO CS & ->set_cs() */

		if ((spi->controller->flags & SPI_CONTROLLER_GPIO_SS) &&

		    spi->controller->set_cs)

			spi->controller->set_cs(spi, !enable);

 * @ctlr:	Pointer to spi_controller device

 *

 * Registers an spi_device for each child node of controller node which

 * represents a valid SPI slave.

 * represents a valid SPI target device.

 */

static void of_register_spi_devices(struct spi_controller *ctlr)

{

	if (!lookup.max_speed_hz &&

	    ACPI_SUCCESS(acpi_get_parent(adev->handle, &parent_handle)) &&

	    device_match_acpi_handle(lookup.ctlr->dev.parent, parent_handle)) {

		/* Apple does not use _CRS but nested devices for SPI slaves */

		/* Apple does not use _CRS but nested devices for SPI target devices */

		acpi_spi_parse_apple_properties(adev, &lookup);

	}

				     SPI_ACPI_ENUMERATE_MAX_DEPTH,

				     acpi_spi_add_device, NULL, ctlr, NULL);

	if (ACPI_FAILURE(status))

		dev_warn(&ctlr->dev, "failed to enumerate SPI slaves\n");

		dev_warn(&ctlr->dev, "failed to enumerate SPI target devices\n");

}

#else

static inline void acpi_register_spi_devices(struct spi_controller *ctlr) {}

	kfree(ctlr);

}

static const struct class spi_master_class = {

static const struct class spi_controller_class = {

	.name		= "spi_master",

	.dev_release	= spi_controller_release,

	.dev_groups	= spi_master_groups,

	.dev_groups	= spi_controller_groups,

};

#ifdef CONFIG_SPI_SLAVE

/**

 * spi_target_abort - abort the ongoing transfer request on an SPI slave

 *		     controller

 * spi_target_abort - abort the ongoing transfer request on an SPI target controller

 * @spi: device used for the current transfer

 */

int spi_target_abort(struct spi_device *spi)

	child = device_find_any_child(&ctlr->dev);

	if (child) {

		/* Remove registered slave */

		/* Remove registered target device */

		device_unregister(child);

		put_device(child);

	}

	if (strcmp(name, "(null)")) {

		/* Register new slave */

		/* Register new target device */

		spi = spi_alloc_device(ctlr);

		if (!spi)

			return -ENOMEM;

static DEVICE_ATTR_RW(slave);

static struct attribute *spi_slave_attrs[] = {

static struct attribute *spi_target_attrs[] = {

	&dev_attr_slave.attr,

	NULL,

};

static const struct attribute_group spi_slave_group = {

	.attrs = spi_slave_attrs,

static const struct attribute_group spi_target_group = {

	.attrs = spi_target_attrs,

};

static const struct attribute_group *spi_slave_groups[] = {

static const struct attribute_group *spi_target_groups[] = {

	&spi_controller_statistics_group,

	&spi_slave_group,

	&spi_target_group,

	NULL,

};

static const struct class spi_slave_class = {

static const struct class spi_target_class = {

	.name		= "spi_slave",

	.dev_release	= spi_controller_release,

	.dev_groups	= spi_slave_groups,

	.dev_groups	= spi_target_groups,

};

#else

extern struct class spi_slave_class;	/* dummy */

extern struct class spi_target_class;	/* dummy */

#endif

/**

 * __spi_alloc_controller - allocate an SPI master or slave controller

 * __spi_alloc_controller - allocate an SPI host or target controller

 * @dev: the controller, possibly using the platform_bus

 * @size: how much zeroed driver-private data to allocate; the pointer to this

 *	memory is in the driver_data field of the returned device, accessible

 *	with spi_controller_get_devdata(); the memory is cacheline aligned;

 *	drivers granting DMA access to portions of their private data need to

 *	round up @size using ALIGN(size, dma_get_cache_alignment()).

 * @slave: flag indicating whether to allocate an SPI master (false) or SPI

 *	slave (true) controller

 * @target: flag indicating whether to allocate an SPI host (false) or SPI target (true)

 *	controller

 * Context: can sleep

 *

 * This call is used only by SPI controller drivers, which are the

 * Return: the SPI controller structure on success, else NULL.

 */

struct spi_controller *__spi_alloc_controller(struct device *dev,

					      unsigned int size, bool slave)

					      unsigned int size, bool target)

{

	struct spi_controller	*ctlr;

	size_t ctlr_size = ALIGN(sizeof(*ctlr), dma_get_cache_alignment());

	mutex_init(&ctlr->add_lock);

	ctlr->bus_num = -1;

	ctlr->num_chipselect = 1;

	ctlr->slave = slave;

	if (IS_ENABLED(CONFIG_SPI_SLAVE) && slave)

		ctlr->dev.class = &spi_slave_class;

	ctlr->target = target;

	if (IS_ENABLED(CONFIG_SPI_SLAVE) && target)

		ctlr->dev.class = &spi_target_class;

	else

		ctlr->dev.class = &spi_master_class;

		ctlr->dev.class = &spi_controller_class;

	ctlr->dev.parent = dev;

	pm_suspend_ignore_children(&ctlr->dev, true);

	spi_controller_set_devdata(ctlr, (void *)ctlr + ctlr_size);

 * __devm_spi_alloc_controller - resource-managed __spi_alloc_controller()

 * @dev: physical device of SPI controller

 * @size: how much zeroed driver-private data to allocate

 * @slave: whether to allocate an SPI master (false) or SPI slave (true)

 * @target: whether to allocate an SPI host (false) or SPI target (true) controller

 * Context: can sleep

 *

 * Allocate an SPI controller and automatically release a reference on it

 */

struct spi_controller *__devm_spi_alloc_controller(struct device *dev,

						   unsigned int size,

						   bool slave)

						   bool target)

{

	struct spi_controller **ptr, *ctlr;

	if (!ptr)

		return NULL;

	ctlr = __spi_alloc_controller(dev, size, slave);

	ctlr = __spi_alloc_controller(dev, size, target);

	if (ctlr) {

		ctlr->devm_allocated = true;

		*ptr = ctlr;

EXPORT_SYMBOL_GPL(__devm_spi_alloc_controller);

/**

 * spi_get_gpio_descs() - grab chip select GPIOs for the master

 * @ctlr: The SPI master to grab GPIO descriptors for

 * spi_get_gpio_descs() - grab chip select GPIOs for the controller

 * @ctlr: The SPI controller to grab GPIO descriptors for

 */

static int spi_get_gpio_descs(struct spi_controller *ctlr)

{

	int id;

	mutex_lock(&board_lock);

	id = idr_alloc(&spi_master_idr, ctlr, start, end, GFP_KERNEL);

	id = idr_alloc(&spi_controller_idr, ctlr, start, end, GFP_KERNEL);

	mutex_unlock(&board_lock);

	if (WARN(id < 0, "couldn't get idr"))

		return id == -ENOSPC ? -EBUSY : id;

	spi_destroy_queue(ctlr);

free_bus_id:

	mutex_lock(&board_lock);

	idr_remove(&spi_master_idr, ctlr->bus_num);

	idr_remove(&spi_controller_idr, ctlr->bus_num);

	mutex_unlock(&board_lock);

	return status;

}

}

/**

 * devm_spi_register_controller - register managed SPI host or target

 *	controller

 * devm_spi_register_controller - register managed SPI host or target controller

 * @dev:    device managing SPI controller

 * @ctlr: initialized controller, originally from spi_alloc_host() or

 *	spi_alloc_target()

}

/**

 * spi_unregister_controller - unregister SPI master or slave controller

 * spi_unregister_controller - unregister SPI host or target controller

 * @ctlr: the controller being unregistered

 * Context: can sleep

 *

	/* First make sure that this controller was ever added */

	mutex_lock(&board_lock);

	found = idr_find(&spi_master_idr, id);

	found = idr_find(&spi_controller_idr, id);

	mutex_unlock(&board_lock);

	if (ctlr->queued) {

		if (spi_destroy_queue(ctlr))

	/* Free bus id */

	mutex_lock(&board_lock);

	if (found == ctlr)

		idr_remove(&spi_master_idr, id);

		idr_remove(&spi_controller_idr, id);

	mutex_unlock(&board_lock);

	if (IS_ENABLED(CONFIG_SPI_DYNAMIC))

/**

 * spi_bus_lock - obtain a lock for exclusive SPI bus usage

 * @ctlr: SPI bus master that should be locked for exclusive bus access

 * @ctlr: SPI bus controller that should be locked for exclusive bus access

 * Context: can sleep

 *

 * This call may only be used from a context that may sleep.  The sleep

/**

 * spi_bus_unlock - release the lock for exclusive SPI bus usage

 * @ctlr: SPI bus master that was locked for exclusive bus access

 * @ctlr: SPI bus controller that was locked for exclusive bus access

 * Context: can sleep

 *

 * This call may only be used from a context that may sleep.  The sleep

{

	struct device *dev;

	dev = class_find_device_by_of_node(&spi_master_class, node);

	dev = class_find_device_by_of_node(&spi_controller_class, node);

	if (!dev && IS_ENABLED(CONFIG_SPI_SLAVE))

		dev = class_find_device_by_of_node(&spi_slave_class, node);

		dev = class_find_device_by_of_node(&spi_target_class, node);

	if (!dev)

		return NULL;

{

	struct device *dev;

	dev = class_find_device(&spi_master_class, NULL, adev,

	dev = class_find_device(&spi_controller_class, NULL, adev,

				spi_acpi_controller_match);

	if (!dev && IS_ENABLED(CONFIG_SPI_SLAVE))

		dev = class_find_device(&spi_slave_class, NULL, adev,

		dev = class_find_device(&spi_target_class, NULL, adev,

					spi_acpi_controller_match);

	if (!dev)

		return NULL;

	if (status < 0)

		goto err1;

	status = class_register(&spi_master_class);

	status = class_register(&spi_controller_class);

	if (status < 0)

		goto err2;

	if (IS_ENABLED(CONFIG_SPI_SLAVE)) {

		status = class_register(&spi_slave_class);

		status = class_register(&spi_target_class);

		if (status < 0)

			goto err3;

	}

	return 0;

err3:

	class_unregister(&spi_master_class);

	class_unregister(&spi_controller_class);

err2:

	bus_unregister(&spi_bus_type);

err1:

struct spi_offload_config;

/*

 * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,

 * INTERFACES between SPI controller-side drivers and SPI target protocol handlers,

 * and SPI infrastructure.

 */

extern const struct bus_type spi_bus_type;

						  struct spi_transfer *xfer);

/**

 * struct spi_device - Controller side proxy for an SPI slave device

 * struct spi_device - Controller side proxy for an SPI target device

 * @dev: Driver model representation of the device.

 * @controller: SPI controller used with the device.

 * @max_speed_hz: Maximum clock rate to be used with this chip

 * @pcpu_statistics: statistics for the spi_device

 * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array

 *

 * A @spi_device is used to interchange data between an SPI slave

 * A @spi_device is used to interchange data between an SPI target device

 * (usually a discrete chip) and CPU memory.

 *

 * In @dev, the platform_data is used to hold information about this

			spi_unregister_driver)

/**

 * struct spi_controller - interface to SPI master or slave controller

 * struct spi_controller - interface to SPI host or target controller

 * @dev: device interface to this driver

 * @list: link with the global spi_controller list

 * @bus_num: board-specific (and often SOC-specific) identifier for a

 *	given SPI controller.

 * @num_chipselect: chipselects are used to distinguish individual

 *	SPI slaves, and are numbered from zero to num_chipselects.

 *	each slave has a chipselect signal, but it's common that not

 *	every chipselect is connected to a slave.

 *	SPI targets, and are numbered from zero to num_chipselects.

 *	each target has a chipselect signal, but it's common that not

 *	every chipselect is connected to a target.

 * @dma_alignment: SPI controller constraint on DMA buffers alignment.

 * @mode_bits: flags understood by this controller driver

 * @buswidth_override_bits: flags to override for this controller driver

 *	must fail if an unrecognized or unsupported mode is requested.

 *	It's always safe to call this unless transfers are pending on

 *	the device whose settings are being modified.

 * @set_cs_timing: optional hook for SPI devices to request SPI master

 * @set_cs_timing: optional hook for SPI devices to request SPI

 * controller for configuring specific CS setup time, hold time and inactive

 * delay in terms of clock counts

 * @transfer: adds a message to the controller's transfer queue.

 *

 * The driver for an SPI controller manages access to those devices through

 * a queue of spi_message transactions, copying data between CPU memory and

 * an SPI slave device.  For each such message it queues, it calls the

 * an SPI target device.  For each such message it queues, it calls the

 * message's completion function when the transaction completes.

 */

struct spi_controller {

#define SPI_CONTROLLER_NO_TX		BIT(2)	/* Can't do buffer write */

#define SPI_CONTROLLER_MUST_RX		BIT(3)	/* Requires rx */

#define SPI_CONTROLLER_MUST_TX		BIT(4)	/* Requires tx */

#define SPI_CONTROLLER_GPIO_SS		BIT(5)	/* GPIO CS must select slave */

#define SPI_CONTROLLER_GPIO_SS		BIT(5)	/* GPIO CS must select target device */

#define SPI_CONTROLLER_SUSPENDED	BIT(6)	/* Currently suspended */

	/*

	 * The spi-controller has multi chip select capability and can

	 * + To a given spi_device, message queueing is pure FIFO

	 *

	 * + The controller's main job is to process its message queue,

	 *   selecting a chip (for masters), then transferring data

	 *   selecting a chip (for controllers), then transferring data

	 * + If there are multiple spi_device children, the i/o queue

	 *   arbitration algorithm is unspecified (round robin, FIFO,

	 *   priority, reservations, preemption, etc)

/* The SPI driver core manages memory for the spi_controller classdev */

extern struct spi_controller *__spi_alloc_controller(struct device *host,

						unsigned int size, bool slave);

						unsigned int size, bool target);

static inline struct spi_controller *spi_alloc_host(struct device *dev,

						    unsigned int size)

struct spi_controller *__devm_spi_alloc_controller(struct device *dev,

						   unsigned int size,

						   bool slave);

						   bool target);

static inline struct spi_controller *devm_spi_alloc_host(struct device *dev,

							 unsigned int size)

 *	purposefully (instead of setting to spi_transfer->len - 1) to denote

 *	that a transfer-level snapshot taken from within the driver may still

 *	be of higher quality.

 * @ptp_sts: Pointer to a memory location held by the SPI slave device where a

 * @ptp_sts: Pointer to a memory location held by the SPI target device where a

 *	PTP system timestamp structure may lie. If drivers use PIO or their

 *	hardware has some sort of assist for retrieving exact transfer timing,

 *	they can (and should) assert @ptp_sts_supported and populate this

 *	structure using the ptp_read_system_*ts helper functions.

 *	The timestamp must represent the time at which the SPI slave device has

 *	The timestamp must represent the time at which the SPI target device has

 *	processed the word, i.e. the "pre" timestamp should be taken before

 *	transmitting the "pre" word, and the "post" timestamp after receiving

 *	transmit confirmation from the controller for the "post" word.

	 * bus_num is board specific and matches the bus_num of some

	 * spi_controller that will probably be registered later.

	 *

	 * chip_select reflects how this chip is wired to that master;

	 * chip_select reflects how this chip is wired to that controller;

	 * it's less than num_chipselect.

	 */

	u16		bus_num;