Commit 91e5bfe3 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 

Pull dmaengine updates from Vinod Koul:
 "The dmaengine subsystem updates for this cycle consist of a new driver
  (Microchip) along with couple of yaml binding conversions, core api
  updates and bunch of driver updates etc.

  New HW support:

   - Microchip sama7d65 dma controller

   - Yaml conversion of atmel dma binding and Freescale Elo DMA
     Controller binding

  Core:

   - Remove device_prep_dma_imm_data() API as users are removed

   - Reduce scope of some less frequently used DMA request channel APIs
     with aim to cleanup these in future

  Updates:

   - Drop Fenghua Yu from idxd maintainers, as he changed jobs

   - AMD ptdma support for multiqueue and ae4dma deprecated PCI IDs
     removal"

* tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (29 commits)
  dmaengine: ptdma: Utilize the AE4DMA engine's multi-queue functionality
  dmaengine: ae4dma: Use the MSI count and its corresponding IRQ number
  dmaengine: ae4dma: Remove deprecated PCI IDs
  dmaengine: Remove device_prep_dma_imm_data from struct dma_device
  dmaengine: ti: edma: support sw triggered chans in of_edma_xlate()
  dmaengine: ti: k3-udma: Enable second resource range for BCDMA and PKTDMA
  dmaengine: fsl-edma: free irq correctly in remove path
  dmaengine: fsl-edma: cleanup chan after dma_async_device_unregister
  dt-bindings: dma: snps,dw-axi-dmac: Allow devices to be marked as noncoherent
  dmaengine: dmatest: Fix dmatest waiting less when interrupted
  dt-bindings: dma: Convert fsl,elo*-dma to YAML
  dt-bindings: dma: fsl-mxs-dma: Add compatible string for i.MX8 chips
  dmaengine: Fix typo in comment
  dmaengine: ti: k3-udma-glue: Drop skip_fdq argument from k3_udma_glue_reset_rx_chn
  dmaengine: bcm2835-dma: fix warning when CONFIG_PM=n
  dt-bindings: dma: fsl,edma: Add i.MX94 support
  dt-bindings: dma: atmel: add microchip,sama7d65-dma
  dmaengine: img-mdc: remove incorrect of_match_ptr annotation
  dmaengine: idxd: Delete unnecessary NULL check
  dmaengine: pxa: Enable compile test
  ...
parents e63a1653 65654398

Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Atmel Direct Memory Access Controller (DMA)



maintainers:

  - Ludovic Desroches <ludovic.desroches@microchip.com>



description:

  The Atmel Direct Memory Access Controller (DMAC) transfers data from a source

  peripheral to a destination peripheral over one or more AMBA buses. One channel

  is required for each source/destination pair. In the most basic configuration,

  the DMAC has one master interface and one channel. The master interface reads

  the data from a source and writes it to a destination. Two AMBA transfers are

  required for each DMAC data transfer. This is also known as a dual-access transfer.

  The DMAC is programmed via the APB interface.



properties:

  compatible:

    enum:

      - atmel,at91sam9g45-dma

      - atmel,at91sam9rl-dma



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  "#dma-cells":

    description:

      Must be <2>, used to represent the number of integer cells in the dma

      property of client devices. The two cells in order are

      1. The first cell represents the channel number.

      2. The second cell is 0 for RX and 1 for TX transfers.

    const: 2



  clocks:

    maxItems: 1



  clock-names:

    const: dma_clk



required:

  - compatible

  - reg

  - interrupts

  - "#dma-cells"

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    dma-controller@ffffec00 {

        compatible = "atmel,at91sam9g45-dma";

        reg = <0xffffec00 0x200>;

        interrupts = <21>;

        #dma-cells = <2>;

        clocks = <&pmc 2 20>;

        clock-names = "dma_clk";

    };



...

Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml

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@@ -32,6 +32,9 @@ properties: 
              - microchip,sam9x60-dma

              - microchip,sam9x7-dma

          - const: atmel,sama5d4-dma

      - items:

          - const: microchip,sama7d65-dma

          - const: microchip,sama7g5-dma



  "#dma-cells":

    description: |

Documentation/devicetree/bindings/dma/atmel-dma.txt

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* Atmel Direct Memory Access Controller (DMA)



Required properties:

- compatible: Should be "atmel,<chip>-dma".

- reg: Should contain DMA registers location and length.

- interrupts: Should contain DMA interrupt.

- #dma-cells: Must be <2>, used to represent the number of integer cells in

the dmas property of client devices.



Example:



dma0: dma@ffffec00 {

	compatible = "atmel,at91sam9g45-dma";

	reg = <0xffffec00 0x200>;

	interrupts = <21>;

	#dma-cells = <2>;

};



DMA clients connected to the Atmel DMA controller must use the format

described in the dma.txt file, using a three-cell specifier for each channel:

a phandle plus two integer cells.

The three cells in order are:



1. A phandle pointing to the DMA controller.

2. The memory interface (16 most significant bits), the peripheral interface

(16 less significant bits).

3. Parameters for the at91 DMA configuration register which are device

dependent:

  - bit 7-0: peripheral identifier for the hardware handshaking interface. The

  identifier can be different for tx and rx.

  - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.



Example:



i2c0@i2c@f8010000 {

	compatible = "atmel,at91sam9x5-i2c";

	reg = <0xf8010000 0x100>;

	interrupts = <9 4 6>;

	dmas = <&dma0 1 7>,

	       <&dma0 1 8>;

	dma-names = "tx", "rx";

};

Documentation/devicetree/bindings/dma/fsl,edma.yaml

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@@ -27,6 +27,14 @@ properties: 
          - fsl,imx93-edma4

          - fsl,imx95-edma5

          - nxp,s32g2-edma

      - items:

          - enum:

              - fsl,imx94-edma3

          - const: fsl,imx93-edma3

      - items:

          - enum:

              - fsl,imx94-edma5

          - const: fsl,imx95-edma5

      - items:

          - const: fsl,ls1028a-edma

          - const: fsl,vf610-edma

Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale Elo DMA Controller



maintainers:

  - J. Neuschäfer <j.ne@posteo.net>



description:

  This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx

  series chips such as mpc8315, mpc8349, mpc8379 etc.



properties:

  compatible:

    items:

      - enum:

          - fsl,mpc8313-dma

          - fsl,mpc8315-dma

          - fsl,mpc8323-dma

          - fsl,mpc8347-dma

          - fsl,mpc8349-dma

          - fsl,mpc8360-dma

          - fsl,mpc8377-dma

          - fsl,mpc8378-dma

          - fsl,mpc8379-dma

      - const: fsl,elo-dma



  reg:

    items:

      - description:

          DMA General Status Register, i.e. DGSR which contains status for

          all the 4 DMA channels.



  cell-index:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: Controller index. 0 for controller @ 0x8100.



  ranges: true



  "#address-cells":

    const: 1



  "#size-cells":

    const: 1



  interrupts:

    maxItems: 1

    description: Controller interrupt.



required:

  - compatible

  - reg



patternProperties:

  "^dma-channel@[0-9a-f]+$":

    type: object

    additionalProperties: false



    properties:

      compatible:

        oneOf:

          # native DMA channel

          - items:

              - enum:

                  - fsl,mpc8315-dma-channel

                  - fsl,mpc8323-dma-channel

                  - fsl,mpc8347-dma-channel

                  - fsl,mpc8349-dma-channel

                  - fsl,mpc8360-dma-channel

                  - fsl,mpc8377-dma-channel

                  - fsl,mpc8378-dma-channel

                  - fsl,mpc8379-dma-channel

              - const: fsl,elo-dma-channel



          # audio DMA channel, see fsl,ssi.yaml

          - const: fsl,ssi-dma-channel



      reg:

        maxItems: 1



      cell-index:

        description: DMA channel index starts at 0.



      interrupts:

        maxItems: 1

        description:

          Per-channel interrupt. Only necessary if no controller interrupt has

          been provided.



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    dma@82a8 {

        compatible = "fsl,mpc8349-dma", "fsl,elo-dma";

        reg = <0x82a8 4>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges = <0 0x8100 0x1a4>;

        interrupts = <71 IRQ_TYPE_LEVEL_LOW>;

        cell-index = <0>;



        dma-channel@0 {

            compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";

            reg = <0 0x80>;

            cell-index = <0>;

            interrupts = <71 IRQ_TYPE_LEVEL_LOW>;

        };



        dma-channel@80 {

            compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";

            reg = <0x80 0x80>;

            cell-index = <1>;

            interrupts = <71 IRQ_TYPE_LEVEL_LOW>;

        };



        dma-channel@100 {

            compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";

            reg = <0x100 0x80>;

            cell-index = <2>;

            interrupts = <71 IRQ_TYPE_LEVEL_LOW>;

        };



        dma-channel@180 {

            compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";

            reg = <0x180 0x80>;

            cell-index = <3>;

            interrupts = <71 IRQ_TYPE_LEVEL_LOW>;

        };

    };



...