Unverified Commit 922b9937 authored by Mark Brown's avatar Mark Brown
Browse files

regulator: mt6315: add regulator supplies 

Chen-Yu Tsai <wenst@chromium.org> says:

This series is part of a broader collection of regulator related
cleanups for MediaTek Chromebooks. This one covers the MT6315 PMIC.

Patch 1 adds the names of the power supply inputs to the binding.

Patch 2 adds the supply names from the DT binding change in patch 1
to the regulator descriptions in the driver. This patch has a
checkpatch.pl warnings, but I wonder if it's because the context size
for checking complex macros is not large enough.

Device tree changes will be sent separately. The goal is to get the
regulator tree as complete as possible. This includes adding supply
names to other regulator DT bindings, and adding all the supply links
to the existing DTs.
parents 5a623ef7 292d64fb

.mailmap

+2 −0
Original line number Diff line number Diff line
@@ -316,6 +316,7 @@ Hans Verkuil <hverkuil@kernel.org> <hverkuil-cisco@xs4all.nl> 
Hans Verkuil <hverkuil@kernel.org> <hansverk@cisco.com>

Hao Ge <hao.ge@linux.dev> <gehao@kylinos.cn>

Harry Yoo <harry.yoo@oracle.com> <42.hyeyoo@gmail.com>

Harry Yoo <harry@kernel.org> <harry.yoo@oracle.com>

Heiko Carstens <hca@linux.ibm.com> <h.carstens@de.ibm.com>

Heiko Carstens <hca@linux.ibm.com> <heiko.carstens@de.ibm.com>

Heiko Stuebner <heiko@sntech.de> <heiko.stuebner@bqreaders.com>
@@ -587,6 +588,7 @@ Morten Welinder <terra@gnome.org> 
Morten Welinder <welinder@anemone.rentec.com>

Morten Welinder <welinder@darter.rentec.com>

Morten Welinder <welinder@troll.com>

Muhammad Usama Anjum <usama.anjum@arm.com> <usama.anjum@collabora.com>

Mukesh Ojha <quic_mojha@quicinc.com> <mojha@codeaurora.org>

Muna Sinada <quic_msinada@quicinc.com> <msinada@codeaurora.org>

Murali Nalajala <quic_mnalajal@quicinc.com> <mnalajal@codeaurora.org>

Documentation/PCI/pcieaer-howto.rst

+10 −0
Original line number Diff line number Diff line
@@ -85,6 +85,16 @@ In the example, 'Requester ID' means the ID of the device that sent 
the error message to the Root Port. Please refer to PCIe specs for other

fields.



The 'TLP Header' is the prefix/header of the TLP that caused the error

in raw hex format. To decode the TLP Header into human-readable form

one may use tlp-tool:



https://github.com/mmpg-x86/tlp-tool



Example usage::



  curl -L https://git.kernel.org/linus/2ca1c94ce0b6 | rtlp-tool --aer



AER Ratelimits

--------------

Documentation/core-api/dma-attributes.rst

+30 −8
Original line number Diff line number Diff line
@@ -149,11 +149,33 @@ For architectures that require cache flushing for DMA coherence 
DMA_ATTR_MMIO will not perform any cache flushing. The address

provided must never be mapped cacheable into the CPU.



DMA_ATTR_CPU_CACHE_CLEAN

------------------------



This attribute indicates the CPU will not dirty any cacheline overlapping this

DMA_FROM_DEVICE/DMA_BIDIRECTIONAL buffer while it is mapped. This allows

multiple small buffers to safely share a cacheline without risk of data

corruption, suppressing DMA debug warnings about overlapping mappings.

All mappings sharing a cacheline should have this attribute.
 
DMA_ATTR_DEBUGGING_IGNORE_CACHELINES

------------------------------------



This attribute indicates that CPU cache lines may overlap for buffers mapped

with DMA_FROM_DEVICE or DMA_BIDIRECTIONAL.



Such overlap may occur when callers map multiple small buffers that reside

within the same cache line. In this case, callers must guarantee that the CPU

will not dirty these cache lines after the mappings are established. When this

condition is met, multiple buffers can safely share a cache line without risking

data corruption.



All mappings that share a cache line must set this attribute to suppress DMA

debug warnings about overlapping mappings.



DMA_ATTR_REQUIRE_COHERENT

-------------------------



DMA mapping requests with the DMA_ATTR_REQUIRE_COHERENT fail on any

system where SWIOTLB or cache management is required. This should only

be used to support uAPI designs that require continuous HW DMA

coherence with userspace processes, for example RDMA and DRM. At a

minimum the memory being mapped must be userspace memory from

pin_user_pages() or similar.



Drivers should consider using dma_mmap_pages() instead of this

interface when building their uAPIs, when possible.



It must never be used in an in-kernel driver that only works with

kernel memory.

Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml

+12 −0
Original line number Diff line number Diff line
@@ -25,6 +25,15 @@ properties: 
  reg:

    maxItems: 1



  pvdd1-supply:

    description: Supply for regulator vbuck1

  pvdd2-supply:

    description: Supply for regulator vbuck2

  pvdd3-supply:

    description: Supply for regulator vbuck3

  pvdd4-supply:

    description: Supply for regulator vbuck4



  regulators:

    type: object

    description: List of regulators and its properties
@@ -49,8 +58,11 @@ examples: 
    pmic@6 {

      compatible = "mediatek,mt6315-regulator";

      reg = <0x6 0>;

      pvdd1-supply = <&pp4200_z2>;

      pvdd3-supply = <&pp4200_z2>;



      regulators {



        vbuck1 {

          regulator-min-microvolt = <300000>;

          regulator-max-microvolt = <1193750>;

Documentation/devicetree/bindings/sound/rockchip-spdif.yaml

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ properties: 
          - const: rockchip,rk3066-spdif

      - items:

          - enum:

              - rockchip,rk3576-spdif

              - rockchip,rk3588-spdif

          - const: rockchip,rk3568-spdif