Commit 927127cd authored by Raj Victor's avatar Raj Victor Committed by Tony Nguyen
Browse files

ice: Adjust the VSI/Aggregator layers 



Adjust the VSI/Aggregator layers based on the number of logical layers
supported by the FW. Currently the VSI and Aggregator layers are
fixed based on the 9 layer scheduler tree layout. Due to performance
reasons the number of layers of the scheduler tree is changing from
9 to 5. It requires a readjustment of these VSI/Aggregator layer values.

Signed-off-by: default avatarRaj Victor <victor.raj@intel.com>
Co-developed-by: default avatarMichal Wilczynski <michal.wilczynski@intel.com>
Signed-off-by: default avatarMichal Wilczynski <michal.wilczynski@intel.com>
Signed-off-by: default avatarMateusz Polchlopek <mateusz.polchlopek@intel.com>
Tested-by: default avatarPucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
parent 91427e6d

drivers/net/ethernet/intel/ice/ice_sched.c

+19 −18
Original line number Diff line number Diff line
@@ -1128,12 +1128,11 @@ u8 ice_sched_get_vsi_layer(struct ice_hw *hw) 
	 *     5 or less       sw_entry_point_layer

	 */

	/* calculate the VSI layer based on number of layers. */

	if (hw->num_tx_sched_layers > ICE_VSI_LAYER_OFFSET + 1) {

		u8 layer = hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;



		if (layer > hw->sw_entry_point_layer)

			return layer;

	}

	if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS)

		return hw->num_tx_sched_layers - ICE_VSI_LAYER_OFFSET;

	else if (hw->num_tx_sched_layers == ICE_SCHED_5_LAYERS)

		/* qgroup and VSI layers are same */

		return hw->num_tx_sched_layers - ICE_QGRP_LAYER_OFFSET;

	return hw->sw_entry_point_layer;

}
@@ -1150,12 +1149,9 @@ u8 ice_sched_get_agg_layer(struct ice_hw *hw) 
	 *     7 or less       sw_entry_point_layer

	 */

	/* calculate the aggregator layer based on number of layers. */

	if (hw->num_tx_sched_layers > ICE_AGG_LAYER_OFFSET + 1) {

		u8 layer = hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET;



		if (layer > hw->sw_entry_point_layer)

			return layer;

	}

	if (hw->num_tx_sched_layers == ICE_SCHED_9_LAYERS)

		return hw->num_tx_sched_layers - ICE_AGG_LAYER_OFFSET;

	else

		return hw->sw_entry_point_layer;

}
@@ -1510,10 +1506,11 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 
{

	struct ice_sched_node *vsi_node, *qgrp_node;

	struct ice_vsi_ctx *vsi_ctx;

	u8 qgrp_layer, vsi_layer;

	u16 max_children;

	u8 qgrp_layer;



	qgrp_layer = ice_sched_get_qgrp_layer(pi->hw);

	vsi_layer = ice_sched_get_vsi_layer(pi->hw);

	max_children = pi->hw->max_children[qgrp_layer];



	vsi_ctx = ice_get_vsi_ctx(pi->hw, vsi_handle);
@@ -1524,6 +1521,12 @@ ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 
	if (!vsi_node)

		return NULL;



	/* If the queue group and VSI layer are same then queues

	 * are all attached directly to VSI

	 */

	if (qgrp_layer == vsi_layer)

		return vsi_node;



	/* get the first queue group node from VSI sub-tree */

	qgrp_node = ice_sched_get_first_node(pi, vsi_node, qgrp_layer);

	while (qgrp_node) {
@@ -3199,7 +3202,7 @@ ice_sched_add_rl_profile(struct ice_port_info *pi, 
	u8 profile_type;

	int status;



	if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)

	if (!pi || layer_num >= pi->hw->num_tx_sched_layers)

		return NULL;

	switch (rl_type) {

	case ICE_MIN_BW:
@@ -3215,8 +3218,6 @@ ice_sched_add_rl_profile(struct ice_port_info *pi, 
		return NULL;

	}



	if (!pi)

		return NULL;

	hw = pi->hw;

	list_for_each_entry(rl_prof_elem, &pi->rl_prof_list[layer_num],

			    list_entry)
@@ -3446,7 +3447,7 @@ ice_sched_rm_rl_profile(struct ice_port_info *pi, u8 layer_num, u8 profile_type, 
	struct ice_aqc_rl_profile_info *rl_prof_elem;

	int status = 0;



	if (layer_num >= ICE_AQC_TOPO_MAX_LEVEL_NUM)

	if (layer_num >= pi->hw->num_tx_sched_layers)

		return -EINVAL;

	/* Check the existing list for RL profile */

	list_for_each_entry(rl_prof_elem, &pi->rl_prof_list[layer_num],