Unverified Commit 9276bcc2 authored by Riana Tauro's avatar Riana Tauro Committed by Rodrigo Vivi
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drm/xe: Standardize power gate registers 



Standardize power gate registers

No functional changes

v2: change commit message (Rodrigo)

Signed-off-by: default avatarRiana Tauro <riana.tauro@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240524070916.143022-2-riana.tauro@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 5c9464e2

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+3 −5
Original line number Diff line number Diff line
@@ -316,11 +316,9 @@ 


#define FORCEWAKE_GT				XE_REG(0xa188)



#define PG_ENABLE				XE_REG(0xa210)

#define   VD2_MFXVDENC_POWERGATE_ENABLE		REG_BIT(8)

#define   VD2_HCP_POWERGATE_ENABLE		REG_BIT(7)

#define   VD0_MFXVDENC_POWERGATE_ENABLE		REG_BIT(4)

#define   VD0_HCP_POWERGATE_ENABLE		REG_BIT(3)

#define POWERGATE_ENABLE			XE_REG(0xa210)

#define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))

#define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))



#define CTC_MODE				XE_REG(0xa26c)

#define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)

drivers/gpu/drm/xe/xe_gt_idle.c

+1 −1
Original line number Diff line number Diff line
@@ -202,7 +202,7 @@ void xe_gt_idle_disable_c6(struct xe_gt *gt) 
	xe_device_assert_mem_access(gt_to_xe(gt));

	xe_force_wake_assert_held(gt_to_fw(gt), XE_FORCEWAKE_ALL);



	xe_mmio_write32(gt, PG_ENABLE, 0);

	xe_mmio_write32(gt, POWERGATE_ENABLE, 0);

	xe_mmio_write32(gt, RC_CONTROL, 0);

	xe_mmio_write32(gt, RC_STATE, 0);

}

drivers/gpu/drm/xe/xe_wa.c

+5 −5
Original line number Diff line number Diff line
@@ -238,11 +238,11 @@ static const struct xe_rtp_entry_sr gt_was[] = { 
	},

	{ XE_RTP_NAME("14020316580"),

	  XE_RTP_RULES(MEDIA_VERSION(1301)),

	  XE_RTP_ACTIONS(CLR(PG_ENABLE,

			     VD0_HCP_POWERGATE_ENABLE |

			     VD0_MFXVDENC_POWERGATE_ENABLE |

			     VD2_HCP_POWERGATE_ENABLE |

			     VD2_MFXVDENC_POWERGATE_ENABLE)),

	  XE_RTP_ACTIONS(CLR(POWERGATE_ENABLE,

			     VDN_HCP_POWERGATE_ENABLE(0) |

			     VDN_MFXVDENC_POWERGATE_ENABLE(0) |

			     VDN_HCP_POWERGATE_ENABLE(2) |

			     VDN_MFXVDENC_POWERGATE_ENABLE(2))),

	},

	{ XE_RTP_NAME("14019449301"),

	  XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),