Commit 92c6a707 authored by Bairavi Alagappan's avatar Bairavi Alagappan Committed by Herbert Xu
Browse files

crypto: qat - remove access to parity register for QAT GEN4 



The firmware already handles parity errors reported by the accelerators
by clearing them through the corresponding SSMSOFTERRORPARITY register.
To ensure consistent behavior and prevent race conditions between the
driver and firmware, remove the logic that checks the SSMSOFTERRORPARITY
registers.

Additionally, change the return type of the function
adf_handle_rf_parr_err() to void, as it consistently returns false.
Parity errors are recoverable and do not necessitate a device reset.

Fixes: 895f7d53 ("crypto: qat - add handling of errors from ERRSOU2 for QAT GEN4")
Signed-off-by: default avatarBairavi Alagappan <bairavix.alagappan@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent f9555d18

drivers/crypto/intel/qat/qat_common/adf_gen4_ras.c

+5 −52
Original line number Diff line number Diff line
@@ -1043,63 +1043,16 @@ static bool adf_handle_ssmcpppar_err(struct adf_accel_dev *accel_dev, 
	return reset_required;

}



static bool adf_handle_rf_parr_err(struct adf_accel_dev *accel_dev,

static void adf_handle_rf_parr_err(struct adf_accel_dev *accel_dev,

				   void __iomem *csr, u32 iastatssm)

{

	struct adf_dev_err_mask *err_mask = GET_ERR_MASK(accel_dev);

	u32 reg;



	if (!(iastatssm & ADF_GEN4_IAINTSTATSSM_SSMSOFTERRORPARITY_BIT))

		return false;



	reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_SRC);

	reg &= ADF_GEN4_SSMSOFTERRORPARITY_SRC_BIT;

	if (reg) {

		ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);

		ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_SRC, reg);

	}



	reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_ATH_CPH);

	reg &= err_mask->parerr_ath_cph_mask;

	if (reg) {

		ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);

		ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_ATH_CPH, reg);

	}



	reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_CPR_XLT);

	reg &= err_mask->parerr_cpr_xlt_mask;

	if (reg) {

		ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);

		ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_CPR_XLT, reg);

	}



	reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_DCPR_UCS);

	reg &= err_mask->parerr_dcpr_ucs_mask;

	if (reg) {

		ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);

		ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_DCPR_UCS, reg);

	}

		return;



	reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_PKE);

	reg &= err_mask->parerr_pke_mask;

	if (reg) {

	ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);

		ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_PKE, reg);

	}



	if (err_mask->parerr_wat_wcp_mask) {

		reg = ADF_CSR_RD(csr, ADF_GEN4_SSMSOFTERRORPARITY_WAT_WCP);

		reg &= err_mask->parerr_wat_wcp_mask;

		if (reg) {

			ADF_RAS_ERR_CTR_INC(accel_dev->ras_errors, ADF_RAS_UNCORR);

			ADF_CSR_WR(csr, ADF_GEN4_SSMSOFTERRORPARITY_WAT_WCP,

				   reg);

		}

	}



	dev_err(&GET_DEV(accel_dev), "Slice ssm soft parity error reported");



	return false;

	return;

}



static bool adf_handle_ser_err_ssmsh(struct adf_accel_dev *accel_dev,
@@ -1171,8 +1124,8 @@ static bool adf_handle_iaintstatssm(struct adf_accel_dev *accel_dev, 
	reset_required |= adf_handle_slice_hang_error(accel_dev, csr, iastatssm);

	reset_required |= adf_handle_spppar_err(accel_dev, csr, iastatssm);

	reset_required |= adf_handle_ssmcpppar_err(accel_dev, csr, iastatssm);

	reset_required |= adf_handle_rf_parr_err(accel_dev, csr, iastatssm);

	reset_required |= adf_handle_ser_err_ssmsh(accel_dev, csr, iastatssm);

	adf_handle_rf_parr_err(accel_dev, csr, iastatssm);



	ADF_CSR_WR(csr, ADF_GEN4_IAINTSTATSSM, iastatssm);