Commit 92e2bd56 authored by Vasant Hegde's avatar Vasant Hegde Committed by Joerg Roedel
Browse files

iommu/amd: Introduce iommu_dev_data.flags to track device capabilities 



Currently we use struct iommu_dev_data.iommu_v2 to keep track of the device
ATS, PRI, and PASID capabilities. But these capabilities can be enabled
independently (except PRI requires ATS support). Hence, replace
the iommu_v2 variable with a flags variable, which keep track of the device
capabilities.

From commit 9bf49e36 ("PCI/ATS: Handle sharing of PF PRI Capability
with all VFs"), device PRI/PASID is shared between PF and any associated
VFs. Hence use pci_pri_supported() and pci_pasid_features() instead of
pci_find_ext_capability() to check device PRI/PASID support.

Signed-off-by: default avatarVasant Hegde <vasant.hegde@amd.com>
Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Reviewed-by: default avatarJerry Snitselaar <jsnitsel@redhat.com>
Link: https://lore.kernel.org/r/20230921092147.5930-13-vasant.hegde@amd.com


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 739eb255

drivers/iommu/amd/amd_iommu_types.h

+2 −1
Original line number Diff line number Diff line
@@ -811,7 +811,8 @@ struct iommu_dev_data { 
	struct protection_domain *domain; /* Domain the device is bound to */

	struct device *dev;

	u16 devid;			  /* PCI Device ID */

	bool iommu_v2;			  /* Device can make use of IOMMUv2 */



	u32 flags;			  /* Holds AMD_IOMMU_DEVICE_FLAG_<*> */

	int ats_qdep;

	u8 ats_enabled  :1;		  /* ATS state */

	u8 pri_tlp      :1;		  /* PASID TLB required for

drivers/iommu/amd/iommu.c

+28 −18
Original line number Diff line number Diff line
@@ -319,24 +319,34 @@ static struct iommu_group *acpihid_device_group(struct device *dev) 
	return entry->group;

}



static bool pci_iommuv2_capable(struct pci_dev *pdev)

static inline bool pdev_pasid_supported(struct iommu_dev_data *dev_data)

{

	static const int caps[] = {

		PCI_EXT_CAP_ID_PRI,

		PCI_EXT_CAP_ID_PASID,

	};

	int i, pos;

	return (dev_data->flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP);

}



	if (!pci_ats_supported(pdev))

		return false;

static u32 pdev_get_caps(struct pci_dev *pdev)

{

	int features;

	u32 flags = 0;



	for (i = 0; i < 2; ++i) {

		pos = pci_find_ext_capability(pdev, caps[i]);

		if (pos == 0)

			return false;

	if (pci_ats_supported(pdev))

		flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;



	if (pci_pri_supported(pdev))

		flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;



	features = pci_pasid_features(pdev);

	if (features >= 0) {

		flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;



		if (features & PCI_PASID_CAP_EXEC)

			flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;



		if (features & PCI_PASID_CAP_PRIV)

			flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;

	}



	return true;

	return flags;

}



/*
@@ -396,8 +406,8 @@ static int iommu_init_device(struct amd_iommu *iommu, struct device *dev) 
	 * it'll be forced to go into translation mode.

	 */

	if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&

	    dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {

		dev_data->iommu_v2 = amd_iommu_gt_ppr_supported();

	    dev_is_pci(dev) && amd_iommu_gt_ppr_supported()) {

		dev_data->flags = pdev_get_caps(to_pci_dev(dev));

	}



	dev_iommu_priv_set(dev, dev_data);
@@ -1850,7 +1860,7 @@ static int attach_device(struct device *dev, 
			goto out;

		}



		if (dev_data->iommu_v2) {

		if (pdev_pasid_supported(dev_data)) {

			if (pdev_pri_ats_enable(pdev) != 0)

				goto out;
@@ -1916,7 +1926,7 @@ static void detach_device(struct device *dev) 
	if (!dev_is_pci(dev))

		goto out;



	if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)

	if (domain->flags & PD_IOMMUV2_MASK && pdev_pasid_supported(dev_data))

		pdev_iommuv2_disable(to_pci_dev(dev));

	else if (dev_data->ats_enabled)

		pci_disable_ats(to_pci_dev(dev));
@@ -2471,7 +2481,7 @@ static int amd_iommu_def_domain_type(struct device *dev) 
	 *    and require remapping.

	 *  - SNP is enabled, because it prohibits DTE[Mode]=0.

	 */

	if (dev_data->iommu_v2 &&

	if (pdev_pasid_supported(dev_data) &&

	    !cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&

	    !amd_iommu_snp_en) {

		return IOMMU_DOMAIN_IDENTITY;