Commit 930fd7fe authored by Ido Schimmel's avatar Ido Schimmel Committed by Jakub Kicinski
Browse files

mlxsw: spectrum_ethtool: Add support for 100Gb/s per lane link modes 



The Spectrum-4 ASIC supports 100Gb/s per lane link modes, but the only
one currently supported by the driver is 800Gb/s over eight lanes.

Add support for 100Gb/s over one lane, 200Gb/s over two lanes and
400Gb/s over four lanes.

Signed-off-by: default avatarIdo Schimmel <idosch@nvidia.com>
Reviewed-by: default avatarPetr Machata <petrm@nvidia.com>
Signed-off-by: default avatarPetr Machata <petrm@nvidia.com>
Reviewed-by: default avatarJacob Keller <jacob.e.keller@intel.com>
Link: https://lore.kernel.org/r/1d77830f6abcc4f0d57a7f845e5a6d97a75a434b.1712667750.git.petrm@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 7e36c337

drivers/net/ethernet/mellanox/mlxsw/reg.h

+3 −0
Original line number Diff line number Diff line
@@ -4786,8 +4786,11 @@ MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR	BIT(8)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4		BIT(9)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2		BIT(10)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_1_100GBASE_CR_KR		BIT(11)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4		BIT(12)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_2_200GBASE_CR2_KR2		BIT(13)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8				BIT(15)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_4_400GBASE_CR4_KR4		BIT(16)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8				BIT(19)



/* reg_ptys_ext_eth_proto_cap

drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c

+60 −0
Original line number Diff line number Diff line
@@ -1648,6 +1648,18 @@ mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = { 
#define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_100gaui_1_100gbase_cr_kr[] = {

	ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,

	ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,

	ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,

	ETHTOOL_LINK_MODE_100000baseCR_Full_BIT,

	ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,

};



#define MLXSW_SP2_MASK_ETHTOOL_100GAUI_1_100GBASE_CR_KR_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_1_100gbase_cr_kr)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {

	ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
@@ -1660,6 +1672,18 @@ mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = { 
#define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_200gaui_2_200gbase_cr2_kr2[] = {

	ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,

	ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,

	ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,

	ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,

	ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT,

};



#define MLXSW_SP2_MASK_ETHTOOL_200GAUI_2_200GBASE_CR2_KR2_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_2_200gbase_cr2_kr2)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_400gaui_8[] = {

	ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
@@ -1672,6 +1696,18 @@ mlxsw_sp2_mask_ethtool_400gaui_8[] = { 
#define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_400gaui_4_400gbase_cr4_kr4[] = {

	ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,

	ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,

	ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,

	ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,

	ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT,

};



#define MLXSW_SP2_MASK_ETHTOOL_400GAUI_4_400GBASE_CR4_KR4_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_4_400gbase_cr4_kr4)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_800gaui_8[] = {

	ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT,
@@ -1816,6 +1852,14 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.speed		= SPEED_100000,

		.width		= 2,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_1_100GBASE_CR_KR,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_100gaui_1_100gbase_cr_kr,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_100GAUI_1_100GBASE_CR_KR_LEN,

		.mask_sup_width	= MLXSW_SP_PORT_MASK_WIDTH_1X,

		.speed		= SPEED_100000,

		.width		= 1,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
@@ -1825,6 +1869,14 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.speed		= SPEED_200000,

		.width		= 4,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_2_200GBASE_CR2_KR2,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_200gaui_2_200gbase_cr2_kr2,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_200GAUI_2_200GBASE_CR2_KR2_LEN,

		.mask_sup_width	= MLXSW_SP_PORT_MASK_WIDTH_2X,

		.speed		= SPEED_200000,

		.width		= 2,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_400gaui_8,
@@ -1833,6 +1885,14 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.speed		= SPEED_400000,

		.width		= 8,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_4_400GBASE_CR4_KR4,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_400gaui_4_400gbase_cr4_kr4,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_400GAUI_4_400GBASE_CR4_KR4_LEN,

		.mask_sup_width	= MLXSW_SP_PORT_MASK_WIDTH_4X,

		.speed		= SPEED_400000,

		.width		= 4,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_800gaui_8,