Loading arch/mips/au1000/common/int-handler.S +2 −1 Original line number Diff line number Diff line Loading @@ -64,5 +64,6 @@ NESTED(au1000_IRQ, PT_SIZE, sp) 5: move a0, sp j spurious_interrupt jal spurious_interrupt j ret_from_irq END(au1000_IRQ) arch/mips/ddb5xxx/ddb5476/int-handler.S +2 −1 Original line number Diff line number Diff line Loading @@ -54,7 +54,8 @@ .set reorder /* wrong alarm or masked ... */ // j spurious_interrupt // jal spurious_interrupt // j ret_from_irq move a0, sp jal vrc5476_irq_dispatch j ret_from_irq Loading arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c +1 −3 Original line number Diff line number Diff line Loading @@ -80,8 +80,6 @@ vrc5476_irq_init(u32 base) asmlinkage void vrc5476_irq_dispatch(struct pt_regs *regs) { extern void spurious_interrupt(void); u32 mask; int nile4_irq; Loading @@ -107,5 +105,5 @@ vrc5476_irq_dispatch(struct pt_regs *regs) return; } } spurious_interrupt(); spurious_interrupt(regs); } arch/mips/ddb5xxx/ddb5477/int-handler.S +2 −2 Original line number Diff line number Diff line Loading @@ -44,8 +44,8 @@ .set reorder /* wrong alarm or masked ... */ j spurious_interrupt nop jal spurious_interrupt j ret_from_irq END(ddb5477_handle_int) .align 5 Loading arch/mips/dec/int-handler.S +3 −1 Original line number Diff line number Diff line Loading @@ -282,7 +282,9 @@ fpu: #endif spurious: j spurious_interrupt jal spurious_interrupt nop j ret_from_irq nop END(decstation_handle_int) Loading Loading
arch/mips/au1000/common/int-handler.S +2 −1 Original line number Diff line number Diff line Loading @@ -64,5 +64,6 @@ NESTED(au1000_IRQ, PT_SIZE, sp) 5: move a0, sp j spurious_interrupt jal spurious_interrupt j ret_from_irq END(au1000_IRQ)
arch/mips/ddb5xxx/ddb5476/int-handler.S +2 −1 Original line number Diff line number Diff line Loading @@ -54,7 +54,8 @@ .set reorder /* wrong alarm or masked ... */ // j spurious_interrupt // jal spurious_interrupt // j ret_from_irq move a0, sp jal vrc5476_irq_dispatch j ret_from_irq Loading
arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c +1 −3 Original line number Diff line number Diff line Loading @@ -80,8 +80,6 @@ vrc5476_irq_init(u32 base) asmlinkage void vrc5476_irq_dispatch(struct pt_regs *regs) { extern void spurious_interrupt(void); u32 mask; int nile4_irq; Loading @@ -107,5 +105,5 @@ vrc5476_irq_dispatch(struct pt_regs *regs) return; } } spurious_interrupt(); spurious_interrupt(regs); }
arch/mips/ddb5xxx/ddb5477/int-handler.S +2 −2 Original line number Diff line number Diff line Loading @@ -44,8 +44,8 @@ .set reorder /* wrong alarm or masked ... */ j spurious_interrupt nop jal spurious_interrupt j ret_from_irq END(ddb5477_handle_int) .align 5 Loading
arch/mips/dec/int-handler.S +3 −1 Original line number Diff line number Diff line Loading @@ -282,7 +282,9 @@ fpu: #endif spurious: j spurious_interrupt jal spurious_interrupt nop j ret_from_irq nop END(decstation_handle_int) Loading