Unverified Commit 9343aaba authored by Conor Dooley's avatar Conor Dooley Committed by Alexandre Ghiti
Browse files

RISC-V: separate Zbb optimisations requiring and not requiring toolchain support 



It seems a bit ridiculous to require toolchain support for BPF to
assemble Zbb instructions, so move the dependency on toolchain support
for Zbb optimisations out of the Kconfig option and to the callsites.

Zbb support has always depended on alternatives, so while adjusting the
config options guarding optimisations, remove any checks for
whether or not alternatives are enabled.

Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Reviewed-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20241024-chump-freebase-d26b6d81af33@spud


Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
parent 6216182f

arch/riscv/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -664,12 +664,12 @@ config RISCV_ISA_ZBA 


config RISCV_ISA_ZBB

	bool "Zbb extension support for bit manipulation instructions"

	depends on TOOLCHAIN_HAS_ZBB

	depends on RISCV_ALTERNATIVE

	default y

	help

	   Add support for enabling optimisations in the kernel when the

	   Zbb extension is detected at boot.

	   Zbb extension is detected at boot. Some optimisations may

	   additionally depend on toolchain support for Zbb.



	   The Zbb extension provides instructions to accelerate a number

	   of bit-specific operations (count bit population, sign extending,

arch/riscv/include/asm/arch_hweight.h

+3 −3
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 


static __always_inline unsigned int __arch_hweight32(unsigned int w)

{

#ifdef CONFIG_RISCV_ISA_ZBB

#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)

	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,

				      RISCV_ISA_EXT_ZBB, 1)

			  : : : : legacy);
@@ -50,7 +50,7 @@ static inline unsigned int __arch_hweight8(unsigned int w) 
#if BITS_PER_LONG == 64

static __always_inline unsigned long __arch_hweight64(__u64 w)

{

# ifdef CONFIG_RISCV_ISA_ZBB

#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)

	asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,

				      RISCV_ISA_EXT_ZBB, 1)

			  : : : : legacy);

arch/riscv/include/asm/bitops.h

+2 −2
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 
#include <asm/barrier.h>

#include <asm/bitsperlong.h>



#if !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE)

#if !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE)

#include <asm-generic/bitops/__ffs.h>

#include <asm-generic/bitops/__fls.h>

#include <asm-generic/bitops/ffs.h>
@@ -175,7 +175,7 @@ static __always_inline int variable_fls(unsigned int x) 
	 variable_fls(x_);					\

})



#endif /* !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE) */

#endif /* !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE) */



#include <asm-generic/bitops/ffz.h>

#include <asm-generic/bitops/fls64.h>

arch/riscv/include/asm/checksum.h

+1 −2
Original line number Diff line number Diff line
@@ -49,8 +49,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) 
	 * ZBB only saves three instructions on 32-bit and five on 64-bit so not

	 * worth checking if supported without Alternatives.

	 */

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&

	    IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {

		unsigned long fold_temp;



		asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0,

arch/riscv/lib/csum.c

+3 −18
Original line number Diff line number Diff line
@@ -40,12 +40,7 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, 
	uproto = (__force unsigned int)htonl(proto);

	sum += uproto;



	/*

	 * Zbb support saves 4 instructions, so not worth checking without

	 * alternatives if supported

	 */

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&

	    IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {

		unsigned long fold_temp;



		/*
@@ -157,12 +152,7 @@ do_csum_with_alignment(const unsigned char *buff, int len) 
	csum = do_csum_common(ptr, end, data);



#ifdef CC_HAS_ASM_GOTO_TIED_OUTPUT

	/*

	 * Zbb support saves 6 instructions, so not worth checking without

	 * alternatives if supported

	 */

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&

	    IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {

		unsigned long fold_temp;



		/*
@@ -244,12 +234,7 @@ do_csum_no_alignment(const unsigned char *buff, int len) 
	end = (const unsigned long *)(buff + len);

	csum = do_csum_common(ptr, end, data);



	/*

	 * Zbb support saves 6 instructions, so not worth checking without

	 * alternatives if supported

	 */

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&

	    IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {

		unsigned long fold_temp;



		/*