Commit 935e486b authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Matt Roper
Browse files

drm/i915/cdclk: Re-use bxt_cdclk_ctl() when sanitizing 



The function bxt_cdclk_ctl() is responsible for deriving the value for
CDCLK_CTL; use it instead of repeating the same logic.

v2:
  - Use a better commit message body by making it more self-contained
    and not referring to stuff from the subject line. (Matt)

Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240105140538.183553-5-gustavo.sousa@intel.com
parent ebb9c424

drivers/gpu/drm/i915/display/intel_cdclk.c

+3 −23
Original line number Diff line number Diff line
@@ -2051,7 +2051,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)

{

	u32 cdctl, expected;

	int cdclk, clock, vco;

	int cdclk, vco;



	intel_update_cdclk(dev_priv);

	intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
@@ -2076,6 +2076,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 
	 * so sanitize this register.

	 */

	cdctl = intel_de_read(dev_priv, CDCLK_CTL);

	expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE);



	/*

	 * Let's ignore the pipe field, since BIOS could have configured the
@@ -2083,28 +2084,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) 
	 * (PIPE_NONE).

	 */

	cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);



	if (DISPLAY_VER(dev_priv) >= 20)

		expected = MDCLK_SOURCE_SEL_CDCLK_PLL;

	else

		expected = skl_cdclk_decimal(cdclk);



	/* Figure out what CD2X divider we should be using for this cdclk */

	if (HAS_CDCLK_SQUASH(dev_priv))

		clock = dev_priv->display.cdclk.hw.vco / 2;

	else

		clock = dev_priv->display.cdclk.hw.cdclk;



	expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock,

					   dev_priv->display.cdclk.hw.vco);



	/*

	 * Disable SSA Precharge when CD clock frequency < 500 MHz,

	 * enable otherwise.

	 */

	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&

	    dev_priv->display.cdclk.hw.cdclk >= 500000)

		expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;

	expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);



	if (cdctl == expected)

		/* All well; nothing to sanitize */