Commit 9361cace authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 's390-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux 

Pull more s390 updates from Alexander Gordeev:

 - Compile the decompressor with -Wno-pointer-sign flag to avoid a clang
   warning

 - Fix incomplete conversion to flag output macros in __xsch(), to avoid
   always zero return value instead of the expected condition code

 - Remove superfluous newlines from inline assemblies to improve
   compiler inlining decisions

 - Expose firmware provided UID Checking state in sysfs regardless of
   the device presence or state

 - CIO does not unregister subchannels when the attached device is
   invalid or unavailable. Update the purge function to remove I/O
   subchannels if the device number is found on cio_ignore list

 - Consolidate PAI crypto allocation and cleanup paths

 - The uv_get_secret_metadata() function has been removed some few
   months ago, remove also the function mention it in a comment

* tag 's390-6.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux:
  s390/uv: Fix comment of uv_find_secret() function
  s390/pai_crypto: Consolidate PAI crypto allocation and cleanup paths
  s390/cio: Update purge function to unregister the unused subchannels
  s390/pci: Expose firmware provided UID Checking state in sysfs
  s390: Remove superfluous newlines from inline assemblies
  s390/cio/ioasm: Fix __xsch() condition code handling
  s390: Add -Wno-pointer-sign to KBUILD_CFLAGS_DECOMPRESSOR
parents f6db358d deabb34b

arch/s390/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ endif 
KBUILD_CFLAGS_DECOMPRESSOR := $(CLANG_FLAGS) -m64 -O2 -mpacked-stack -std=gnu11

KBUILD_CFLAGS_DECOMPRESSOR += -DDISABLE_BRANCH_PROFILING -D__NO_FORTIFY

KBUILD_CFLAGS_DECOMPRESSOR += -D__DECOMPRESSOR

KBUILD_CFLAGS_DECOMPRESSOR += -Wno-pointer-sign

KBUILD_CFLAGS_DECOMPRESSOR += -fno-delete-null-pointer-checks -msoft-float -mbackchain

KBUILD_CFLAGS_DECOMPRESSOR += -fno-asynchronous-unwind-tables

KBUILD_CFLAGS_DECOMPRESSOR += -ffreestanding

arch/s390/hypfs/hypfs_sprp.c

+1 −1
Original line number Diff line number Diff line
@@ -27,7 +27,7 @@ static inline unsigned long __hypfs_sprp_diag304(void *data, unsigned long cmd) 
{

	union register_pair r1 = { .even = virt_to_phys(data), };



	asm volatile("diag %[r1],%[r3],0x304\n"

	asm volatile("diag %[r1],%[r3],0x304"

		     : [r1] "+&d" (r1.pair)

		     : [r3] "d" (cmd)

		     : "memory");

arch/s390/include/asm/ap.h

+9 −9
Original line number Diff line number Diff line
@@ -143,7 +143,7 @@ static inline struct ap_queue_status ap_tapq(ap_qid_t qid, 
		"	lghi	2,0\n"			/* 0 into gr2 */

		"	.insn	rre,0xb2af0000,0,0\n"	/* PQAP(TAPQ) */

		"	lgr	%[reg1],1\n"		/* gr1 (status) into reg1 */

		"	lgr	%[reg2],2\n"		/* gr2 into reg2 */

		"	lgr	%[reg2],2"		/* gr2 into reg2 */

		: [reg1] "=&d" (reg1.value), [reg2] "=&d" (reg2)

		: [qid] "d" (qid)

		: "cc", "0", "1", "2");
@@ -186,7 +186,7 @@ static inline struct ap_queue_status ap_rapq(ap_qid_t qid, int fbit) 
	asm volatile(

		"	lgr	0,%[reg0]\n"		/* qid arg into gr0 */

		"	.insn	rre,0xb2af0000,0,0\n"	/* PQAP(RAPQ) */

		"	lgr	%[reg1],1\n"		/* gr1 (status) into reg1 */

		"	lgr	%[reg1],1"		/* gr1 (status) into reg1 */

		: [reg1] "=&d" (reg1.value)

		: [reg0] "d" (reg0)

		: "cc", "0", "1");
@@ -211,7 +211,7 @@ static inline struct ap_queue_status ap_zapq(ap_qid_t qid, int fbit) 
	asm volatile(

		"	lgr	0,%[reg0]\n"		/* qid arg into gr0 */

		"	.insn	rre,0xb2af0000,0,0\n"	/* PQAP(ZAPQ) */

		"	lgr	%[reg1],1\n"		/* gr1 (status) into reg1 */

		"	lgr	%[reg1],1"		/* gr1 (status) into reg1 */

		: [reg1] "=&d" (reg1.value)

		: [reg0] "d" (reg0)

		: "cc", "0", "1");
@@ -315,7 +315,7 @@ static inline struct ap_queue_status ap_aqic(ap_qid_t qid, 
		"	lgr	1,%[reg1]\n"		/* irq ctrl into gr1 */

		"	lgr	2,%[reg2]\n"		/* ni addr into gr2 */

		"	.insn	rre,0xb2af0000,0,0\n"	/* PQAP(AQIC) */

		"	lgr	%[reg1],1\n"		/* gr1 (status) into reg1 */

		"	lgr	%[reg1],1"		/* gr1 (status) into reg1 */

		: [reg1] "+&d" (reg1.value)

		: [reg0] "d" (reg0), [reg2] "d" (reg2)

		: "cc", "memory", "0", "1", "2");
@@ -363,7 +363,7 @@ static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit, 
		"	lgr	1,%[reg1]\n"		/* qact in info into gr1 */

		"	.insn	rre,0xb2af0000,0,0\n"	/* PQAP(QACT) */

		"	lgr	%[reg1],1\n"		/* gr1 (status) into reg1 */

		"	lgr	%[reg2],2\n"		/* qact out info into reg2 */

		"	lgr	%[reg2],2"		/* qact out info into reg2 */

		: [reg1] "+&d" (reg1.value), [reg2] "=&d" (reg2)

		: [reg0] "d" (reg0)

		: "cc", "0", "1", "2");
@@ -388,7 +388,7 @@ static inline struct ap_queue_status ap_bapq(ap_qid_t qid) 
	asm volatile(

		"	lgr	0,%[reg0]\n"		/* qid arg into gr0 */

		"	.insn	rre,0xb2af0000,0,0\n"	/* PQAP(BAPQ) */

		"	lgr	%[reg1],1\n"		/* gr1 (status) into reg1 */

		"	lgr	%[reg1],1"		/* gr1 (status) into reg1 */

		: [reg1] "=&d" (reg1.value)

		: [reg0] "d" (reg0)

		: "cc", "0", "1");
@@ -416,7 +416,7 @@ static inline struct ap_queue_status ap_aapq(ap_qid_t qid, unsigned int sec_idx) 
		"	lgr	0,%[reg0]\n"		/* qid arg into gr0 */

		"	lgr	2,%[reg2]\n"		/* secret index into gr2 */

		"	.insn	rre,0xb2af0000,0,0\n"	/* PQAP(AAPQ) */

		"	lgr	%[reg1],1\n"		/* gr1 (status) into reg1 */

		"	lgr	%[reg1],1"		/* gr1 (status) into reg1 */

		: [reg1] "=&d" (reg1.value)

		: [reg0] "d" (reg0), [reg2] "d" (reg2)

		: "cc", "0", "1", "2");
@@ -453,7 +453,7 @@ static inline struct ap_queue_status ap_nqap(ap_qid_t qid, 
		"	lgr	0,%[reg0]\n"  /* qid param in gr0 */

		"0:	.insn	rre,0xb2ad0000,%[nqap_r1],%[nqap_r2]\n"

		"	brc	2,0b\n"       /* handle partial completion */

		"	lgr	%[reg1],1\n"  /* gr1 (status) into reg1 */

		"	lgr	%[reg1],1"    /* gr1 (status) into reg1 */

		: [reg0] "+&d" (reg0), [reg1] "=&d" (reg1.value),

		  [nqap_r2] "+&d" (nqap_r2.pair)

		: [nqap_r1] "d" (nqap_r1.pair)
@@ -518,7 +518,7 @@ static inline struct ap_queue_status ap_dqap(ap_qid_t qid, 
		"	brc	6,0b\n"        /* handle partial complete */

		"2:	lgr	%[reg0],0\n"   /* gr0 (qid + info) into reg0 */

		"	lgr	%[reg1],1\n"   /* gr1 (status) into reg1 */

		"	lgr	%[reg2],2\n"   /* gr2 (res length) into reg2 */

		"	lgr	%[reg2],2"     /* gr2 (res length) into reg2 */

		: [reg0] "+&d" (reg0), [reg1] "=&d" (reg1.value),

		  [reg2] "=&d" (reg2), [rp1] "+&d" (rp1.pair),

		  [rp2] "+&d" (rp2.pair)

arch/s390/include/asm/atomic_ops.h

+14 −14
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ static __always_inline int __atomic_read(const int *ptr) 
	int val;



	asm volatile(

		"	l	%[val],%[ptr]\n"

		"	l	%[val],%[ptr]"

		: [val] "=d" (val) : [ptr] "R" (*ptr));

	return val;

}
@@ -26,11 +26,11 @@ static __always_inline void __atomic_set(int *ptr, int val) 
{

	if (__builtin_constant_p(val) && val >= S16_MIN && val <= S16_MAX) {

		asm volatile(

			"	mvhi	%[ptr],%[val]\n"

			"	mvhi	%[ptr],%[val]"

			: [ptr] "=Q" (*ptr) : [val] "K" (val));

	} else {

		asm volatile(

			"	st	%[val],%[ptr]\n"

			"	st	%[val],%[ptr]"

			: [ptr] "=R" (*ptr) : [val] "d" (val));

	}

}
@@ -40,7 +40,7 @@ static __always_inline long __atomic64_read(const long *ptr) 
	long val;



	asm volatile(

		"	lg	%[val],%[ptr]\n"

		"	lg	%[val],%[ptr]"

		: [val] "=d" (val) : [ptr] "RT" (*ptr));

	return val;

}
@@ -49,11 +49,11 @@ static __always_inline void __atomic64_set(long *ptr, long val) 
{

	if (__builtin_constant_p(val) && val >= S16_MIN && val <= S16_MAX) {

		asm volatile(

			"	mvghi	%[ptr],%[val]\n"

			"	mvghi	%[ptr],%[val]"

			: [ptr] "=Q" (*ptr) : [val] "K" (val));

	} else {

		asm volatile(

			"	stg	%[val],%[ptr]\n"

			"	stg	%[val],%[ptr]"

			: [ptr] "=RT" (*ptr) : [val] "d" (val));

	}

}
@@ -66,7 +66,7 @@ static __always_inline op_type op_name(op_type val, op_type *ptr) \ 
	op_type old;							\

									\

	asm volatile(							\

		op_string "	%[old],%[val],%[ptr]\n"			\

		op_string "	%[old],%[val],%[ptr]"			\

		op_barrier						\

		: [old] "=d" (old), [ptr] "+QS" (*ptr)			\

		: [val] "d" (val) : "cc", "memory");			\
@@ -75,7 +75,7 @@ static __always_inline op_type op_name(op_type val, op_type *ptr) \ 


#define __ATOMIC_OPS(op_name, op_type, op_string)			\

	__ATOMIC_OP(op_name, op_type, op_string, "")			\

	__ATOMIC_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")

	__ATOMIC_OP(op_name##_barrier, op_type, op_string, "\nbcr 14,0")



__ATOMIC_OPS(__atomic_add, int, "laa")

__ATOMIC_OPS(__atomic_and, int, "lan")
@@ -94,14 +94,14 @@ __ATOMIC_OPS(__atomic64_xor, long, "laxg") 
static __always_inline void op_name(op_type val, op_type *ptr)		\

{									\

	asm volatile(							\

		op_string "	%[ptr],%[val]\n"			\

		op_string "	%[ptr],%[val]"				\

		op_barrier						\

		: [ptr] "+QS" (*ptr) : [val] "i" (val) : "cc", "memory");\

}



#define __ATOMIC_CONST_OPS(op_name, op_type, op_string)			\

	__ATOMIC_CONST_OP(op_name, op_type, op_string, "")		\

	__ATOMIC_CONST_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")

	__ATOMIC_CONST_OP(op_name##_barrier, op_type, op_string, "\nbcr 14,0")



__ATOMIC_CONST_OPS(__atomic_add_const, int, "asi")

__ATOMIC_CONST_OPS(__atomic64_add_const, long, "agsi")
@@ -179,7 +179,7 @@ static __always_inline bool op_name(op_type val, op_type *ptr) \ 
	int cc;								\

									\

	asm volatile(							\

		op_string "	%[tmp],%[val],%[ptr]\n"			\

		op_string "	%[tmp],%[val],%[ptr]"			\

		op_barrier						\

		: "=@cc" (cc), [tmp] "=d" (tmp), [ptr] "+QS" (*ptr)	\

		: [val] "d" (val)					\
@@ -189,7 +189,7 @@ static __always_inline bool op_name(op_type val, op_type *ptr) \ 


#define __ATOMIC_TEST_OPS(op_name, op_type, op_string)			\

	__ATOMIC_TEST_OP(op_name, op_type, op_string, "")		\

	__ATOMIC_TEST_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")

	__ATOMIC_TEST_OP(op_name##_barrier, op_type, op_string, "\nbcr 14,0")



__ATOMIC_TEST_OPS(__atomic_add_and_test, int, "laal")

__ATOMIC_TEST_OPS(__atomic64_add_and_test, long, "laalg")
@@ -203,7 +203,7 @@ static __always_inline bool op_name(op_type val, op_type *ptr) \ 
	int cc;								\

									\

	asm volatile(							\

		op_string "	%[ptr],%[val]\n"			\

		op_string "	%[ptr],%[val]"				\

		op_barrier						\

		: "=@cc" (cc), [ptr] "+QS" (*ptr)			\

		: [val] "i" (val)					\
@@ -213,7 +213,7 @@ static __always_inline bool op_name(op_type val, op_type *ptr) \ 


#define __ATOMIC_CONST_TEST_OPS(op_name, op_type, op_string)		\

	__ATOMIC_CONST_TEST_OP(op_name, op_type, op_string, "")		\

	__ATOMIC_CONST_TEST_OP(op_name##_barrier, op_type, op_string, "bcr 14,0\n")

	__ATOMIC_CONST_TEST_OP(op_name##_barrier, op_type, op_string, "\nbcr 14,0")



__ATOMIC_CONST_TEST_OPS(__atomic_add_const_and_test, int, "alsi")

__ATOMIC_CONST_TEST_OPS(__atomic64_add_const_and_test, long, "algsi")

arch/s390/include/asm/barrier.h

+4 −4
Original line number Diff line number Diff line
@@ -18,9 +18,9 @@ 


#ifdef MARCH_HAS_Z196_FEATURES

/* Fast-BCR without checkpoint synchronization */

#define __ASM_BCR_SERIALIZE "bcr 14,0\n"

#define __ASM_BCR_SERIALIZE "bcr 14,0"

#else

#define __ASM_BCR_SERIALIZE "bcr 15,0\n"

#define __ASM_BCR_SERIALIZE "bcr 15,0"

#endif



static __always_inline void bcr_serialize(void)
@@ -69,12 +69,12 @@ static inline unsigned long array_index_mask_nospec(unsigned long index, 


	if (__builtin_constant_p(size) && size > 0) {

		asm("	clgr	%2,%1\n"

		    "	slbgr	%0,%0\n"

		    "	slbgr	%0,%0"

		    :"=d" (mask) : "d" (size-1), "d" (index) :"cc");

		return mask;

	}

	asm("	clgr	%1,%2\n"

	    "	slbgr	%0,%0\n"

	    "	slbgr	%0,%0"

	    :"=d" (mask) : "d" (size), "d" (index) :"cc");

	return ~mask;

}