Commit 9370e430 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.11-2024-08-14' of... 

Merge tag 'amd-drm-fixes-6.11-2024-08-14' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.11-2024-08-14:

amdgpu:
- Fix MES ring buffer overflow
- DCN 3.5 fix
- DCN 3.2.1 fix
- DP MST fix
- Cursor fixes
- JPEG fixes
- Context ops validation
- MES 12 fixes
- VCN 5.0 fix
- HDP fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240814213846.1331827-1-alexander.deucher@amd.com
parents 7c626ce4 23acd1f3

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+3 −0
Original line number Diff line number Diff line
@@ -1057,6 +1057,9 @@ static int amdgpu_cs_patch_ibs(struct amdgpu_cs_parser *p, 
			r = amdgpu_ring_parse_cs(ring, p, job, ib);

			if (r)

				return r;



			if (ib->sa_bo)

				ib->gpu_addr =  amdgpu_sa_bo_gpu_addr(ib->sa_bo);

		} else {

			ib->ptr = (uint32_t *)kptr;

			r = amdgpu_ring_patch_cs_in_place(ring, p, job, ib);

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+8 −0
Original line number Diff line number Diff line
@@ -685,16 +685,24 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 


	switch (args->in.op) {

	case AMDGPU_CTX_OP_ALLOC_CTX:

		if (args->in.flags)

			return -EINVAL;

		r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id);

		args->out.alloc.ctx_id = id;

		break;

	case AMDGPU_CTX_OP_FREE_CTX:

		if (args->in.flags)

			return -EINVAL;

		r = amdgpu_ctx_free(fpriv, id);

		break;

	case AMDGPU_CTX_OP_QUERY_STATE:

		if (args->in.flags)

			return -EINVAL;

		r = amdgpu_ctx_query(adev, fpriv, id, &args->out);

		break;

	case AMDGPU_CTX_OP_QUERY_STATE2:

		if (args->in.flags)

			return -EINVAL;

		r = amdgpu_ctx_query2(adev, fpriv, id, &args->out);

		break;

	case AMDGPU_CTX_OP_GET_STABLE_PSTATE:

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

+24 −2
Original line number Diff line number Diff line
@@ -509,6 +509,16 @@ int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id) 
	int i, r = 0;

	int j;



	if (adev->enable_mes) {

		for (i = 0; i < adev->gfx.num_compute_rings; i++) {

			j = i + xcc_id * adev->gfx.num_compute_rings;

			amdgpu_mes_unmap_legacy_queue(adev,

						   &adev->gfx.compute_ring[j],

						   RESET_QUEUES, 0, 0);

		}

		return 0;

	}



	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)

		return -EINVAL;
@@ -551,6 +561,18 @@ int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id) 
	int i, r = 0;

	int j;



	if (adev->enable_mes) {

		if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) {

			for (i = 0; i < adev->gfx.num_gfx_rings; i++) {

				j = i + xcc_id * adev->gfx.num_gfx_rings;

				amdgpu_mes_unmap_legacy_queue(adev,

						      &adev->gfx.gfx_ring[j],

						      PREEMPT_QUEUES, 0, 0);

			}

		}

		return 0;

	}



	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)

		return -EINVAL;
@@ -995,7 +1017,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg, uint32_t xcc_ 
	if (amdgpu_device_skip_hw_access(adev))

		return 0;



	if (adev->mes.ring.sched.ready)

	if (adev->mes.ring[0].sched.ready)

		return amdgpu_mes_rreg(adev, reg);



	BUG_ON(!ring->funcs->emit_rreg);
@@ -1065,7 +1087,7 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, uint3 
	if (amdgpu_device_skip_hw_access(adev))

		return;



	if (adev->mes.ring.sched.ready) {

	if (adev->mes.ring[0].sched.ready) {

		amdgpu_mes_wreg(adev, reg, v);

		return;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+3 −2
Original line number Diff line number Diff line
@@ -589,7 +589,8 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev) 
		ring = adev->rings[i];

		vmhub = ring->vm_hub;



		if (ring == &adev->mes.ring ||

		if (ring == &adev->mes.ring[0] ||

		    ring == &adev->mes.ring[1] ||

		    ring == &adev->umsch_mm.ring)

			continue;
@@ -761,7 +762,7 @@ void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 
	unsigned long flags;

	uint32_t seq;



	if (adev->mes.ring.sched.ready) {

	if (adev->mes.ring[0].sched.ready) {

		amdgpu_mes_reg_write_reg_wait(adev, reg0, reg1,

					      ref, mask);

		return;

drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

+51 −32
Original line number Diff line number Diff line
@@ -135,9 +135,11 @@ int amdgpu_mes_init(struct amdgpu_device *adev) 
	idr_init(&adev->mes.queue_id_idr);

	ida_init(&adev->mes.doorbell_ida);

	spin_lock_init(&adev->mes.queue_id_lock);

	spin_lock_init(&adev->mes.ring_lock);

	mutex_init(&adev->mes.mutex_hidden);



	for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++)

		spin_lock_init(&adev->mes.ring_lock[i]);



	adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK;

	adev->mes.vmid_mask_mmhub = 0xffffff00;

	adev->mes.vmid_mask_gfxhub = 0xffffff00;
@@ -163,36 +165,38 @@ int amdgpu_mes_init(struct amdgpu_device *adev) 
			adev->mes.sdma_hqd_mask[i] = 0xfc;

	}



	r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs);

	for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {

		r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs[i]);

		if (r) {

			dev_err(adev->dev,

			"(%d) ring trail_fence_offs wb alloc failed\n", r);

		goto error_ids;

				"(%d) ring trail_fence_offs wb alloc failed\n",

				r);

			goto error;

		}

	adev->mes.sch_ctx_gpu_addr =

		adev->wb.gpu_addr + (adev->mes.sch_ctx_offs * 4);

	adev->mes.sch_ctx_ptr =

		(uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs];

		adev->mes.sch_ctx_gpu_addr[i] =

			adev->wb.gpu_addr + (adev->mes.sch_ctx_offs[i] * 4);

		adev->mes.sch_ctx_ptr[i] =

			(uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs[i]];



	r = amdgpu_device_wb_get(adev, &adev->mes.query_status_fence_offs);

		r = amdgpu_device_wb_get(adev,

				 &adev->mes.query_status_fence_offs[i]);

		if (r) {

		amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);

			dev_err(adev->dev,

			"(%d) query_status_fence_offs wb alloc failed\n", r);

		goto error_ids;

			      "(%d) query_status_fence_offs wb alloc failed\n",

			      r);

			goto error;

		}

		adev->mes.query_status_fence_gpu_addr[i] = adev->wb.gpu_addr +

			(adev->mes.query_status_fence_offs[i] * 4);

		adev->mes.query_status_fence_ptr[i] =

			(uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs[i]];

	}

	adev->mes.query_status_fence_gpu_addr =

		adev->wb.gpu_addr + (adev->mes.query_status_fence_offs * 4);

	adev->mes.query_status_fence_ptr =

		(uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs];



	r = amdgpu_device_wb_get(adev, &adev->mes.read_val_offs);

	if (r) {

		amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);

		amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);

		dev_err(adev->dev,

			"(%d) read_val_offs alloc failed\n", r);

		goto error_ids;

		goto error;

	}

	adev->mes.read_val_gpu_addr =

		adev->wb.gpu_addr + (adev->mes.read_val_offs * 4);
@@ -212,10 +216,16 @@ int amdgpu_mes_init(struct amdgpu_device *adev) 
error_doorbell:

	amdgpu_mes_doorbell_free(adev);

error:

	amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);

	amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);

	for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {

		if (adev->mes.sch_ctx_ptr[i])

			amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);

		if (adev->mes.query_status_fence_ptr[i])

			amdgpu_device_wb_free(adev,

				      adev->mes.query_status_fence_offs[i]);

	}

	if (adev->mes.read_val_ptr)

		amdgpu_device_wb_free(adev, adev->mes.read_val_offs);

error_ids:



	idr_destroy(&adev->mes.pasid_idr);

	idr_destroy(&adev->mes.gang_id_idr);

	idr_destroy(&adev->mes.queue_id_idr);
@@ -226,13 +236,22 @@ int amdgpu_mes_init(struct amdgpu_device *adev) 


void amdgpu_mes_fini(struct amdgpu_device *adev)

{

	int i;



	amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj,

			      &adev->mes.event_log_gpu_addr,

			      &adev->mes.event_log_cpu_addr);



	amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs);

	amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs);

	for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {

		if (adev->mes.sch_ctx_ptr[i])

			amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);

		if (adev->mes.query_status_fence_ptr[i])

			amdgpu_device_wb_free(adev,

				      adev->mes.query_status_fence_offs[i]);

	}

	if (adev->mes.read_val_ptr)

		amdgpu_device_wb_free(adev, adev->mes.read_val_offs);



	amdgpu_mes_doorbell_free(adev);



	idr_destroy(&adev->mes.pasid_idr);
@@ -1499,7 +1518,7 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe) 


	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix,

				       sizeof(ucode_prefix));

	if (adev->enable_uni_mes && pipe == AMDGPU_MES_SCHED_PIPE) {

	if (adev->enable_uni_mes) {

		snprintf(fw_name, sizeof(fw_name),

			 "amdgpu/%s_uni_mes.bin", ucode_prefix);

	} else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) &&