Commit 938a3b22 authored by Imre Deak's avatar Imre Deak Committed by Mika Kahola
Browse files

drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming 



The PHY_C20_VDR_HDMI_RATE registers 7:2 bits are reserved and they are
not specified as a must-be-zero field. Accordingly this reserved field
shouldn't be zeroed; to ensure that use an RMW to update the
PHY_C20_HDMI_RATE field (which is bits 1:0 of the register).

Reviewed-by: default avatarLuca Coelho <luciano.coelho@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarMika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20251015125446.3931198-7-mika.kahola@intel.com
parent 4fd60532

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+4 −3
Original line number Diff line number Diff line
@@ -2714,7 +2714,8 @@ static void intel_c20_pll_program(struct intel_display *display, 
		      MB_WRITE_COMMITTED);



	if (!is_dp)

		intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,

		intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,

			      PHY_C20_HDMI_RATE_MASK,

			      intel_c20_get_hdmi_rate(port_clock),

			      MB_WRITE_COMMITTED);

drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -304,6 +304,8 @@ 
#define   PHY_C20_DP_RATE(val)		REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val)

#define   PHY_C20_CONTEXT_TOGGLE	REG_BIT8(0)

#define PHY_C20_VDR_HDMI_RATE		0xD01

#define   PHY_C20_HDMI_RATE_MASK	REG_GENMASK8(1, 0)

#define   PHY_C20_HDMI_RATE(val)	REG_FIELD_PREP8(PHY_C20_HDMI_RATE_MASK, val)

#define PHY_C20_VDR_CUSTOM_WIDTH	0xD02

#define   PHY_C20_CUSTOM_WIDTH_MASK	REG_GENMASK(1, 0)

#define   PHY_C20_CUSTOM_WIDTH(val)	REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)