Commit 93b4ff5b authored by Beleswar Padhi's avatar Beleswar Padhi Committed by Nishanth Menon
Browse files

arm64: dts: ti: k3-am64: Enable remote processors at board level 



Remote Processors defined in top-level AM64x SoC dtsi files are
incomplete without the memory carveouts and mailbox assignments which
are only known at board integration level.

Therefore, disable the remote processors at SoC level and enable them at
board level where above information is available.

Signed-off-by: default avatarBeleswar Padhi <b-padhi@ti.com>
Tested-by: Wadim Egorov <w.egorov@phytec.de> # phycore-am64x
Tested-by: default avatarHari Nagalla <hnagalla@ti.com>
Reviewed-by: default avatarWadim Egorov <w.egorov@phytec.de>
Acked-by: default avatarAndrew Davis <afd@ti.com>
Link: https://patch.msgid.link/20250908142826.1828676-9-b-padhi@ti.com


Signed-off-by: default avatarNishanth Menon <nm@ti.com>
parent f9270495

arch/arm64/boot/dts/ti/k3-am64-main.dtsi

+6 −0
Original line number Diff line number Diff line
@@ -921,6 +921,7 @@ main_r5fss0: r5fss@78000000 { 
			 <0x78200000 0x00 0x78200000 0x08000>,

			 <0x78300000 0x00 0x78300000 0x08000>;

		power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;

		status = "disabled";



		main_r5fss0_core0: r5f@78000000 {

			compatible = "ti,am64-r5f";
@@ -935,6 +936,7 @@ main_r5fss0_core0: r5f@78000000 { 
			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

			status = "disabled";

		};



		main_r5fss0_core1: r5f@78200000 {
@@ -950,6 +952,7 @@ main_r5fss0_core1: r5f@78200000 { 
			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

			status = "disabled";

		};

	};
@@ -963,6 +966,7 @@ main_r5fss1: r5fss@78400000 { 
			 <0x78600000 0x00 0x78600000 0x08000>,

			 <0x78700000 0x00 0x78700000 0x08000>;

		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;

		status = "disabled";



		main_r5fss1_core0: r5f@78400000 {

			compatible = "ti,am64-r5f";
@@ -977,6 +981,7 @@ main_r5fss1_core0: r5f@78400000 { 
			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

			status = "disabled";

		};



		main_r5fss1_core1: r5f@78600000 {
@@ -992,6 +997,7 @@ main_r5fss1_core1: r5f@78600000 { 
			ti,atcm-enable = <1>;

			ti,btcm-enable = <1>;

			ti,loczrama = <1>;

			status = "disabled";

		};

	};

arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -349,28 +349,40 @@ &main_pktdma { 
	bootph-all;

};



&main_r5fss0 {

	status = "okay";

};



&main_r5fss0_core0 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;

	memory-region = <&main_r5fss0_core0_dma_memory_region>,

			<&main_r5fss0_core0_memory_region>;

	status = "okay";

};



&main_r5fss0_core1 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;

	memory-region = <&main_r5fss0_core1_dma_memory_region>,

			<&main_r5fss0_core1_memory_region>;

	status = "okay";

};



&main_r5fss1 {

	status = "okay";

};



&main_r5fss1_core0 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;

	memory-region = <&main_r5fss1_core0_dma_memory_region>,

			<&main_r5fss1_core0_memory_region>;

	status = "okay";

};



&main_r5fss1_core1 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;

	memory-region = <&main_r5fss1_core1_dma_memory_region>,

			<&main_r5fss1_core1_memory_region>;

	status = "okay";

};



&mcu_m4fss {

arch/arm64/boot/dts/ti/k3-am642-evm.dts

+12 −0
Original line number Diff line number Diff line
@@ -764,28 +764,40 @@ mbox_m4_0: mbox-m4-0 { 
	};

};



&main_r5fss0 {

	status = "okay";

};



&main_r5fss0_core0 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;

	memory-region = <&main_r5fss0_core0_dma_memory_region>,

			<&main_r5fss0_core0_memory_region>;

	status = "okay";

};



&main_r5fss0_core1 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;

	memory-region = <&main_r5fss0_core1_dma_memory_region>,

			<&main_r5fss0_core1_memory_region>;

	status = "okay";

};



&main_r5fss1 {

	status = "okay";

};



&main_r5fss1_core0 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;

	memory-region = <&main_r5fss1_core0_dma_memory_region>,

			<&main_r5fss1_core0_memory_region>;

	status = "okay";

};



&main_r5fss1_core1 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;

	memory-region = <&main_r5fss1_core1_dma_memory_region>,

			<&main_r5fss1_core1_memory_region>;

	status = "okay";

};



&mcu_m4fss {

arch/arm64/boot/dts/ti/k3-am642-sk.dts

+12 −0
Original line number Diff line number Diff line
@@ -679,28 +679,40 @@ mbox_m4_0: mbox-m4-0 { 
	};

};



&main_r5fss0 {

	status = "okay";

};



&main_r5fss0_core0 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;

	memory-region = <&main_r5fss0_core0_dma_memory_region>,

			<&main_r5fss0_core0_memory_region>;

	status = "okay";

};



&main_r5fss0_core1 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;

	memory-region = <&main_r5fss0_core1_dma_memory_region>,

			<&main_r5fss0_core1_memory_region>;

	status = "okay";

};



&main_r5fss1 {

	status = "okay";

};



&main_r5fss1_core0 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;

	memory-region = <&main_r5fss1_core0_dma_memory_region>,

			<&main_r5fss1_core0_memory_region>;

	status = "okay";

};



&main_r5fss1_core1 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;

	memory-region = <&main_r5fss1_core1_dma_memory_region>,

			<&main_r5fss1_core1_memory_region>;

	status = "okay";

};



&mcu_m4fss {

arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi

+12 −0
Original line number Diff line number Diff line
@@ -488,28 +488,40 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB0_DRVVBUS */ 
	};

};



&main_r5fss0 {

	status = "okay";

};



&main_r5fss0_core0 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;

	memory-region = <&main_r5fss0_core0_dma_memory_region>,

			<&main_r5fss0_core0_memory_region>;

	status = "okay";

};



&main_r5fss0_core1 {

	mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;

	memory-region = <&main_r5fss0_core1_dma_memory_region>,

			<&main_r5fss0_core1_memory_region>;

	status = "okay";

};



&main_r5fss1 {

	status = "okay";

};



&main_r5fss1_core0 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;

	memory-region = <&main_r5fss1_core0_dma_memory_region>,

			<&main_r5fss1_core0_memory_region>;

	status = "okay";

};



&main_r5fss1_core1 {

	mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;

	memory-region = <&main_r5fss1_core1_dma_memory_region>,

			<&main_r5fss1_core1_memory_region>;

	status = "okay";

};



/* SoC default UART console */