Commit 93beaa98 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.8' of... 

Merge tag 'qcom-clk-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - New drivers to support global, display, gpu, tcsr, and rpmh clocks on
   Qualcomm SM8650
 - Global and RPMh clock support for the Qualcomm X1E80100 SoC
 - Support for the Stromer APCS PLL found in Qualcomm IPQ5018
 - Add a new type of branch clock, with support for controlling separate
   memory control bits, to the Qualcomm clk driver
 - Use new branch type in Qualcomm ECPRI clk driver for QDU1000 and
   QRU1000
 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939
 - Add support for the camera clock controller on Qualcomm SC8280XP
 - Correct PLL configuration in GPU and video clock controllers for
   Qualcomm SM8150
 - Add runtime PM support and a few missing resets to Qualcomm SM8150
   video clock controller
 - Fix configuration of various GCC GDSCs on Qualcomm SM8550
 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver
 - Fix up GPU and display clock controllers PLL configuration settings
   on Qualcomm SM8550

* tag 'qcom-clk-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (41 commits)
  clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config
  clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config
  clk: qcom: dispcc-sm8550: Use the correct PLL configuration function
  clk: qcom: dispcc-sm8550: Update disp PLL settings
  clk: qcom: gpucc-sm8550: Update GPU PLL settings
  clk: qcom: gcc-sm8550: Mark RCGs shared where applicable
  clk: qcom: gcc-sm8550: use collapse-voting for PCIe GDSCs
  clk: qcom: gcc-sm8550: Mark the PCIe GDSCs votable
  clk: qcom: gcc-sm8550: Add the missing RETAIN_FF_ENABLE GDSC flag
  clk: qcom: camcc-sc8280xp: Prevent error pointer dereference
  clk: qcom: videocc-sm8150: Add runtime PM support
  clk: qcom: videocc-sm8150: Add missing PLL config property
  clk: qcom: videocc-sm8150: Update the videocc resets
  dt-bindings: clock: Update the videocc resets for sm8150
  clk: qcom: rpmh: Add support for X1E80100 rpmh clocks
  clk: qcom: Add Global Clock controller (GCC) driver for X1E80100
  dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for X1E80100
  dt-bindings: clock: qcom: Add X1E80100 GCC clocks
  clk: qcom: Add ECPRICC driver support for QDU1000 and QRU1000
  clk: qcom: branch: Add mem ops support for branch2 clocks
  ...
parents b85ea95d 757d1ca1

Documentation/devicetree/bindings/clock/qcom,a53pll.yaml

+1 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ description: 
properties:

  compatible:

    enum:

      - qcom,ipq5018-a53pll

      - qcom,ipq5332-a53pll

      - qcom,ipq6018-a53pll

      - qcom,ipq8074-a53pll

Documentation/devicetree/bindings/clock/qcom,camcc-sm8250.yaml

+4 −14
Original line number Diff line number Diff line
@@ -15,6 +15,9 @@ description: | 


  See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h



allOf:

  - $ref: qcom,gcc.yaml#



properties:

  compatible:

    const: qcom,sm8250-camcc
@@ -33,15 +36,6 @@ properties: 
      - const: bi_tcxo_ao

      - const: sleep_clk



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  power-domains:

    items:

      - description: MMCX power domain
@@ -56,14 +50,10 @@ properties: 


required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false

unevaluatedProperties: false



examples:

  - |

Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml

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+57 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq6018.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on IPQ6018



maintainers:

  - Stephen Boyd <sboyd@kernel.org>

  - Taniya Das <quic_tdas@quicinc.com>

  - Robert Marko <robimarko@gmail.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on IPQ6018.



  See also::

    include/dt-bindings/clock/qcom,gcc-ipq6018.h

    include/dt-bindings/reset/qcom,gcc-ipq6018.h



allOf:

  - $ref: qcom,gcc.yaml#



properties:

  compatible:

    const: qcom,gcc-ipq6018



  clocks:

    items:

      - description: board XO clock

      - description: sleep clock



  clock-names:

    items:

      - const: xo

      - const: sleep_clk



required:

  - compatible

  - clocks

  - clock-names



unevaluatedProperties: false



examples:

  - |

    clock-controller@1800000 {

      compatible = "qcom,gcc-ipq6018";

      reg = <0x01800000 0x80000>;

      clocks = <&xo>, <&sleep_clk>;

      clock-names = "xo", "sleep_clk";

      #clock-cells = <1>;

      #power-domain-cells = <1>;

      #reset-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml

+0 −3
Original line number Diff line number Diff line
@@ -15,8 +15,6 @@ description: | 
  domains.



  See also::

    include/dt-bindings/clock/qcom,gcc-ipq6018.h

    include/dt-bindings/reset/qcom,gcc-ipq6018.h

    include/dt-bindings/clock/qcom,gcc-msm8953.h

    include/dt-bindings/clock/qcom,gcc-mdm9607.h
@@ -26,7 +24,6 @@ allOf: 
properties:

  compatible:

    enum:

      - qcom,gcc-ipq6018

      - qcom,gcc-mdm9607



required:

Documentation/devicetree/bindings/clock/qcom,qdu1000-ecpricc.yaml

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+68 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,qdu1000-ecpricc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm ECPRI Clock & Reset Controller for QDU1000 and QRU1000



maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Imran Shaik <quic_imrashai@quicinc.com>



description: |

  Qualcomm ECPRI Specification V2.0 Common Public Radio Interface clock control

  module which supports the clocks, resets on QDU1000 and QRU1000



  See also:: include/dt-bindings/clock/qcom,qdu1000-ecpricc.h



properties:

  compatible:

    enum:

      - qcom,qdu1000-ecpricc



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Board XO source

      - description: GPLL0 source from GCC

      - description: GPLL1 source from GCC

      - description: GPLL2 source from GCC

      - description: GPLL3 source from GCC

      - description: GPLL4 source from GCC

      - description: GPLL5 source from GCC



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,qdu1000-gcc.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@280000 {

      compatible = "qcom,qdu1000-ecpricc";

      reg = <0x00280000 0x31c00>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>,

               <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>,

               <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>,

               <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>,

               <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>,

               <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };