Unverified Commit 9409d18b authored by Sheetal's avatar Sheetal Committed by Mark Brown
Browse files

ASoC: tegra: set reg_default_cb callback 



Set reg_default_cb so REGCACHE_FLAT can supply zero defaults without
large reg_defaults tables, simplifying cache initialization for
zero-reset registers.

Signed-off-by: default avatarSheetal <sheetal@nvidia.com>
Reviewed-by: default avatarJon Hunter <jonathanh@nvidia.com>
Tested-by: default avatarJon Hunter <jonathanh@nvidia.com>
Link: https://patch.msgid.link/20260123095346.1258556-4-sheetal@nvidia.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 0ba6286a

sound/soc/tegra/tegra186_asrc.c

+1 −0
Original line number Diff line number Diff line
@@ -950,6 +950,7 @@ static const struct regmap_config tegra186_asrc_regmap_config = { 
	.volatile_reg		= tegra186_asrc_volatile_reg,

	.reg_defaults		= tegra186_asrc_reg_defaults,

	.num_reg_defaults	= ARRAY_SIZE(tegra186_asrc_reg_defaults),

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};

sound/soc/tegra/tegra186_dspk.c

+1 −0
Original line number Diff line number Diff line
@@ -467,6 +467,7 @@ static const struct regmap_config tegra186_dspk_regmap = { 
	.volatile_reg		= tegra186_dspk_volatile_reg,

	.reg_defaults		= tegra186_dspk_reg_defaults,

	.num_reg_defaults	= ARRAY_SIZE(tegra186_dspk_reg_defaults),

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};

sound/soc/tegra/tegra210_admaif.c

+3 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ static const struct regmap_config tegra210_admaif_regmap_config = { 
	.volatile_reg		= tegra_admaif_volatile_reg,

	.reg_defaults		= tegra210_admaif_reg_defaults,

	.num_reg_defaults	= TEGRA210_ADMAIF_CHANNEL_COUNT * 6 + 1,

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};
@@ -254,6 +255,7 @@ static const struct regmap_config tegra186_admaif_regmap_config = { 
	.volatile_reg		= tegra_admaif_volatile_reg,

	.reg_defaults		= tegra186_admaif_reg_defaults,

	.num_reg_defaults	= TEGRA186_ADMAIF_CHANNEL_COUNT * 6 + 1,

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};
@@ -267,6 +269,7 @@ static const struct regmap_config tegra264_admaif_regmap_config = { 
	.volatile_reg		= tegra_admaif_volatile_reg,

	.reg_defaults		= tegra264_admaif_reg_defaults,

	.num_reg_defaults	= TEGRA264_ADMAIF_CHANNEL_COUNT * 6 + 1,

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};

sound/soc/tegra/tegra210_adx.c

+2 −0
Original line number Diff line number Diff line
@@ -625,6 +625,7 @@ static const struct regmap_config tegra210_adx_regmap_config = { 
	.volatile_reg		= tegra210_adx_volatile_reg,

	.reg_defaults		= tegra210_adx_reg_defaults,

	.num_reg_defaults	= ARRAY_SIZE(tegra210_adx_reg_defaults),

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};
@@ -638,6 +639,7 @@ static const struct regmap_config tegra264_adx_regmap_config = { 
	.volatile_reg		= tegra264_adx_volatile_reg,

	.reg_defaults		= tegra264_adx_reg_defaults,

	.num_reg_defaults	= ARRAY_SIZE(tegra264_adx_reg_defaults),

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};

sound/soc/tegra/tegra210_ahub.c

+3 −0
Original line number Diff line number Diff line
@@ -2133,6 +2133,7 @@ static const struct regmap_config tegra210_ahub_regmap_config = { 
	.reg_stride		= 4,

	.writeable_reg		= tegra210_ahub_wr_reg,

	.max_register		= TEGRA210_MAX_REGISTER_ADDR,

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};
@@ -2142,6 +2143,7 @@ static const struct regmap_config tegra186_ahub_regmap_config = { 
	.reg_stride		= 4,

	.writeable_reg		= tegra186_ahub_wr_reg,

	.max_register		= TEGRA186_MAX_REGISTER_ADDR,

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};
@@ -2151,6 +2153,7 @@ static const struct regmap_config tegra264_ahub_regmap_config = { 
	.reg_stride		= 4,

	.writeable_reg		= tegra264_ahub_wr_reg,

	.max_register		= TEGRA264_MAX_REGISTER_ADDR,

	.reg_default_cb		= regmap_default_zero_cb,

	.cache_type		= REGCACHE_FLAT,

};