Commit 941327ca authored by Samuel Holland's avatar Samuel Holland Committed by Conor Dooley
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cache: sifive_ccache: Optimize cache flushes 



Fence instructions are required only at the beginning and the end of
a flush operation, not separately for each cache line being flushed.
Speed up cache flushes by about 15% by removing the extra fences.

Signed-off-by: default avatarSamuel Holland <samuel.holland@sifive.com>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 4fab69dd

drivers/cache/sifive_ccache.c

+4 −4
Original line number Diff line number Diff line
@@ -151,16 +151,16 @@ static void ccache_flush_range(phys_addr_t start, size_t len) 
	if (!len)

		return;



	mb();

	mb(); /* complete earlier memory accesses before the cache flush */

	for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;

			line += SIFIVE_CCACHE_LINE_SIZE) {

#ifdef CONFIG_32BIT

		writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);

		writel_relaxed(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);

#else

		writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);

		writeq_relaxed(line, ccache_base + SIFIVE_CCACHE_FLUSH64);

#endif

		mb();

	}

	mb(); /* issue later memory accesses after the cache flush */

}



static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {