Commit 941f0cb6 authored by Jesse.zhang@amd.com's avatar Jesse.zhang@amd.com Committed by Alex Deucher
Browse files

revert "drm/amdgpu/pm: Implement SDMA queue reset for different asic" 



pmfw unified PPSMC_MSG_ResetSDMA definitions for different devices.
PPSMC_MSG_ResetSDMA2 is not needed.

Signed-off-by: default avatarJesse Zhang <jesse.zhang@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent e9b86b84

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c

+9 −21
Original line number Diff line number Diff line
@@ -2833,29 +2833,17 @@ static int smu_v13_0_6_send_rma_reason(struct smu_context *smu) 


static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)

{

	uint32_t smu_program;

	struct amdgpu_device *adev = smu->adev;

	int ret = 0;



	smu_program = (smu->smc_fw_version >> 24) & 0xff;

	switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {

	case IP_VERSION(13, 0, 6):

		if ((smu_program == 7 || smu_program == 0) &&

		    smu_v13_0_6_caps_supported(smu, SMU_CAPS(SDMA_RESET)))

	/* the message is only valid on SMU 13.0.6 with pmfw 85.121.00 and above */

	if ((adev->flags & AMD_IS_APU) ||

		amdgpu_ip_version(adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 6) ||

		smu->smc_fw_version < 0x00557900)

		return 0;



	ret = smu_cmn_send_smc_msg_with_param(smu,

						SMU_MSG_ResetSDMA, inst_mask, NULL);

		else if ((smu_program == 4) &&

			 smu_v13_0_6_caps_supported(smu, SMU_CAPS(SDMA_RESET)))

			ret = smu_cmn_send_smc_msg_with_param(smu,

				      SMU_MSG_ResetSDMA2, inst_mask, NULL);

		break;

	case IP_VERSION(13, 0, 14):

		if (smu_v13_0_6_caps_supported(smu, SMU_CAPS(SDMA_RESET)))

			ret = smu_cmn_send_smc_msg_with_param(smu,

				      SMU_MSG_ResetSDMA2, inst_mask, NULL);

		break;

	default:

		break;

	}



	if (ret)

		dev_err(smu->adev->dev,