Commit 941f538b authored by Matt Roper's avatar Matt Roper
Browse files

drm/xe: Consolidate workaround entries for Wa_16021867713 



Wa_16021867713 applies to every single media IP from 13.00 to 30.02
(inclusive).  We can consolidate the multiple per-version entries down
to a single range entry.

Reviewed-by: default avatarBalasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Link: https://patch.msgid.link/20260220-forupstream-wa_cleanup-v2-4-b12005a05af6@intel.com


Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent 32fbd228

drivers/gpu/drm/xe/xe_wa.c

+8 −30
Original line number Diff line number Diff line
@@ -131,6 +131,8 @@ __diag_push(); 
__diag_ignore_all("-Woverride-init", "Allow field overrides in table");



static const struct xe_rtp_entry_sr gt_was[] = {

	/* Workarounds applying over a range of IPs */



	{ XE_RTP_NAME("14011060649"),

	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1200, 1255),

		       ENGINE_CLASS(VIDEO_DECODE),
@@ -146,6 +148,12 @@ static const struct xe_rtp_entry_sr gt_was[] = { 
	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1260)),

	  XE_RTP_ACTIONS(CLR(MISCCPCTL, DOP_CLOCK_GATE_RENDER_ENABLE))

	},

	{ XE_RTP_NAME("16021867713"),

	  XE_RTP_RULES(MEDIA_VERSION_RANGE(1300, 3002),

		       ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},



	/* DG1 */
@@ -213,12 +221,6 @@ static const struct xe_rtp_entry_sr gt_was[] = { 


	/* Xe_LPM+ */



	{ XE_RTP_NAME("16021867713"),

	  XE_RTP_RULES(MEDIA_VERSION(1300),

		       ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},

	{ XE_RTP_NAME("22016670082"),

	  XE_RTP_RULES(MEDIA_VERSION(1300)),

	  XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
@@ -232,12 +234,6 @@ static const struct xe_rtp_entry_sr gt_was[] = { 
	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},

	{ XE_RTP_NAME("16021867713"),

	  XE_RTP_RULES(MEDIA_VERSION(2000),

		       ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},

	{ XE_RTP_NAME("14019449301"),

	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
@@ -262,12 +258,6 @@ static const struct xe_rtp_entry_sr gt_was[] = { 


	/* Xe2_HPM */



	{ XE_RTP_NAME("16021867713"),

	  XE_RTP_RULES(MEDIA_VERSION(1301),

		       ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},

	{ XE_RTP_NAME("14019449301"),

	  XE_RTP_RULES(MEDIA_VERSION(1301), ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
@@ -291,12 +281,6 @@ static const struct xe_rtp_entry_sr gt_was[] = { 


	/* Xe3_LPM */



	{ XE_RTP_NAME("16021867713"),

	  XE_RTP_RULES(MEDIA_VERSION(3000),

		       ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},

	{ XE_RTP_NAME("16021865536"),

	  XE_RTP_RULES(MEDIA_VERSION(3000),

		       ENGINE_CLASS(VIDEO_DECODE)),
@@ -309,12 +293,6 @@ static const struct xe_rtp_entry_sr gt_was[] = { 
	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},

	{ XE_RTP_NAME("16021867713"),

	  XE_RTP_RULES(MEDIA_VERSION(3002),

		       ENGINE_CLASS(VIDEO_DECODE)),

	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),

	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),

	},

	{ XE_RTP_NAME("14021486841"),

	  XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),

		       ENGINE_CLASS(VIDEO_DECODE)),