Commit 942e02e1 authored by Inochi Amaoto's avatar Inochi Amaoto Committed by Conor Dooley
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dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi 



The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, and
implements the not yet frozen ACLINT spec. This spec seems to be
abandoned, and will not be frozen in the predictable future.
Frozen specs required by the RISC-V maintainers before merging content
relating to those extensions, therefore a generic compatible is not
appropriate.
Instead, add new vendor specific compatible strings to identify mswi of
sg2042 clint.

Signed-off-by: default avatarInochi Amaoto <inochiama@outlook.com>
Signed-off-by: default avatarChen Wang <unicorn_wang@outlook.com>
[conor: re-wrote commit message to drop irrelevant sifive,clint discussion]
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
parent 4734449f

Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device



maintainers:

  - Inochi Amaoto <inochiama@outlook.com>



properties:

  compatible:

    items:

      - enum:

          - sophgo,sg2042-aclint-mswi

      - const: thead,c900-aclint-mswi



  reg:

    maxItems: 1



  interrupts-extended:

    minItems: 1

    maxItems: 4095



additionalProperties: false



required:

  - compatible

  - reg

  - interrupts-extended



examples:

  - |

    interrupt-controller@94000000 {

      compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";

      interrupts-extended = <&cpu1intc 3>,

                            <&cpu2intc 3>,

                            <&cpu3intc 3>,

                            <&cpu4intc 3>;

      reg = <0x94000000 0x00010000>;

    };

...