Commit 94541321 authored by Benjamin Hahn's avatar Benjamin Hahn Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-phyboard-pollux-rdk: Add support for PCIe 



Add support for the Mini PCIe slot.

Signed-off-by: default avatarBenjamin Hahn <B.Hahn@phytec.de>
Reviewed-by: default avatarYannic Moog <y.moog@phytec.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 52e6774a

arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts

+27 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 


/dts-v1/;



#include <dt-bindings/phy/phy-imx8-pcie.h>

#include <dt-bindings/leds/leds-pca9532.h>

#include <dt-bindings/pwm/pwm.h>

#include "imx8mp-phycore-som.dtsi"
@@ -221,6 +222,23 @@ &snvs_pwrkey { 
	status = "okay";

};



&pcie_phy {

	clocks = <&hsio_blk_ctrl>;

	clock-names = "ref";

	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;

	fsl,clkreq-unsupported;

	status = "okay";

};



/* Mini PCIe */

&pcie {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_pcie0>;

	reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;

	vpcie-supply = <&reg_vcc_3v3_sw>;

	status = "okay";

};



&pwm3 {

	status = "okay";

	pinctrl-names = "default";
@@ -405,6 +423,15 @@ MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12 
		>;

	};



	pinctrl_pcie0: pcie0grp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08     0x40

			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10     0x60

			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x60 /* open drain, pull up */

			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14     0x40

		>;

	};



	pinctrl_pwm3: pwm3grp {

		fsl,pins = <

			MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT		0x12